• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.117-123
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• 2013

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.538-541
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• 1998

This paper describes the development of 5.15ns 32kb asynchronous CMOS SRAM using 0.6.mu.m CMOS technology. The proposed high speed embedded SRAM is realized with optimized control circuit and sense amplifier at a power supply of 3V. Using proposed control circuit, the delay time from address input to wordline 'on' is reduced by 33% and mismatch-insensitive sense amplifier can sense a small difference of bit-line voltage fast and stably.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.57-64
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• 2005

In this paper, we develop the common CAD tool that creates the automatically BIST IP by user settings for the convenient test of embedded memory. Previous tools have defect that when memory model is changed, BIST IP must re-designed depending on memory model because existing tools is limited the widely used algorithms. We develop the tool that is created automatic BIST IP. It applies the algorithm according to the memory model which user requests We usually use the multi-port asynchronous SRAM needless to refresh as the embedded memory. However, This work researches on the dual-port SRAM.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.36-47
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• 1998

Low power circuit techniques have been developed to realize the highest possible performance of embedded SRAM at 1V power supply with$0.5\mu\textrm{m}$ single threshold CMOS technology in which the unbalance between NMOS and PMOS threshold voltages is utilized to optimize the low power CMOS IC design. To achieve the best trade-off between the transistor drivability and the subthreshold current increase, the ground potential of memory array is raised to suppressthe subthreshold current. The problems of lower cellstability and bit-line dealy increase due to the enhanced array ground potential are evaluated to be controlled within the allowable range by careful circuit design. 160MHz, 128kb embedded SRAM with 3.4ns access time is demonstrated with the power consumption of 14.8mW in active $21.4{mu}W$ in standby mode at 1V power supply.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.526-529
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V powr supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5.mu.m double-polysilicon and triplemetal CMOS process technology. A die size is 1.78mm*2.13mm.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.67-78
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• 2016

The emerging Spin-Transfer Torque RAM (STT-RAM) is a promising component that can be used to improve the efficiency as a result of its high storage density and low leakage power. However, the state-of-the-art STT-RAM is not ready to replace SRAM technology due to the negative effect of its write operations. The write operations require longer latency and more power than the same operations in SRAM. Therefore, a hybrid cache with SRAM and STT-RAM technologies is proposed to obtain the benefits of STT-RAM while minimizing its negative effects by using SRAM. To efficiently use of the hybrid cache, it is important to place write intensive data onto the cache. Such data should be placed on SRAM to minimize the negative effect. Thus, we propose a technique that optimizes placement of data in main memory. It drives the proper combination of advantages and disadvantages for SRAM and STT-RAM in the hybrid cache. As a result of the proposed technique, write intensive data are loaded to SRAM and read intensive data are loaded to STT-RAM. In addition, our technique also optimizes temporal locality to minimize conflict misses. Therefore, it improves performance and energy consumption of the hybrid cache architecture in a certain range.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.335-336
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• 2008

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.23-29
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• 2004

In this paper, the asynchronous quasi dual-port SRAM employing a single port structure in SRAM embedded SOC (System On Chip) is proposed. External host can access the internal SRAM freely and the data on internal SRAM can be transferred to an another external circuitry without a synchronous signal of an external host, which operates as an asynchronous dual-port SRRAH The performances of the proposed circuits and control structure are verified through the simulation and we fabricated it using a 0.35um CMOS technology. As the results, the chip shows reduced area about 20% and saved power also 20% than conventional architectures.