• The Journal of the Korea Contents Association
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• v.4 no.1
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• pp.49-55
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• 2004

DDoS is an attack type that interfere with normal service by running out network bandwidth, process throughput, and system resource. It can be recognized intuitively by network slowdown and connection impossibility state, but it is necessary to detect DDoS attack by exact and quantitative analysis. In this paper, the exact and efficient DDoS attack detection system which is able to detect traffic flooding by MIB information, and attack traffic by packet analysis is proposed and realized.

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.158-159
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• 2012

Heterogeneous cellular networks can provide high throughput and coverage compare to conventional networks of only macrocell deployment, however it operates regardless of total power consumption, which is a very important issue of modern cellular networks. We propose a policy that control the on/off state of base stations in heterogeneous networks according daily traffic profile. Under this policy, the total power consumed can be significantly reduced when the traffic is low while preserving QoS requirement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Journal of information and communication convergence engineering
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• v.7 no.2
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• pp.185-192
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• 2009

In wireless mesh networks multi-rate technology environment, a mesh node can dynamically modify the data transmission rate on a particular link, in response to link distance, or more accurately, the perceived SNR ratio between neighbor nodes. In such networks, existing route selection schemes use a link quality metric. Thus, these schemes may easily result in the network being overloaded. In this paper, a new route metric is proposed; it considers both per-hop service delay and link quality at mesh nodes. In addition, the Load-Aware AODV (LA-AODV) protocol using the proposed metric is presented. The performance evaluation is performed by simulation using the OPNET simulator. It is demonstrated that the LA-AODV protocol outperforms the existing routing protocols using other existing route metrics in multi-rate WMN environment.

• Genomics & Informatics
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• v.3 no.1
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• pp.39-42
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• 2005

DNA microarray is a high-throughput biomedical technology that monitors gene expression for thousands of genes in parallel. The abundance and complexity of the gene expression data have given rise to a requirement for their systematic management and analysis to support many laboratories performing microarray research. On these demands, we developed Xperanto for integrated data management and analysis using user-friendly web-based interface. Xperanto provides an integrated environment for management and analysis by linking the computational tools and rich sources of biological annotation. With the growing needs of data sharing, it is designed to be compliant to MGED (Microarray Gene Expression Data) standards for microarray data annotation and exchange. Xperanto enables a fast and efficient management of vast amounts of data, and serves as a communication channel among multiple researchers within an emerging interdisciplinary field.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.733-734
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• 2008

In wireless multihop networks, most of on demand routing protocols suffer from performance degradation due to high mobility and channel errors. This problem is more serious as routing path increases. In this paper, we propose a new scheme which can improve network throughput by using distance adaptive packet bursting. The bursting mechanism is to transmit multiple packets after channel acquisition. Through the simulation, we show that our scheme is more efficient than existing methods.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.163-172
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• 1996

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2003.05a
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• pp.744-748
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• 2003

Developing an interactive satellite multi­media system, such as a digital video broadcasting (DVB) return channel via satellite (RCS) system, is gaining popularity over the world To accommodate the increasing traffic demand we are motivated to investigate an alternative for improving return channel utilization We develop an efficient method for optimal packet scheduling in an interactive satellite multimedia system using hybrid CDMA/TDMA channels. We formulate the timeslot-code assignment problem as a binary integer programming (BIP) problem, where the throughput maximization is the objective, and decompose this BIP problem into two sub-problems for the purpose of solution efficiency. With this decomposition, we promote the computational efficiency in finding the optimal solution of the original BIP problem Since 2001, ETRI has been involved in a development project where we have successfully completed an initial system integration test on broadband mobile Internet access via Ku-band channels using the proposed resource allocation algorithm.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.549-552
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• 2003

In this paper, an efficient architecture of a versatile Reed-Solomon (RS) decoder is designed, where the message length k as well as the block length n can be variable. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm(MEA). A new architecture for the MEA is designed for variable values of error correcting capability t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive and the overclocking technique. The decoder can decode a codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications due to its versatility. A versatile RS decoder over GF(2$^{8}$ ) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.