• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권4호
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• pp.1458-1470
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• 2018

In this letter, a new dual-port Multiple-Input Multiple-Output (MIMO) antenna is introduced which has two independent signal feeding ports in a single antenna element to achieve smaller antenna volumes for the 5G mobile applications. The dual-port structure is implemented by adding a cross coupled semi-loop (CCSL) antenna as the secondary radiator to the ground short of inverted-F antenna (IFA). It is found that the port to port isolation is not deteriorated when an IFA and CCSL is combined to form a dual-port structure. The isolation property of the proposed antenna is compared with a polarization diversity based dual-port antenna proposed in the literature [9]. The operating frequency range is 3.3-4.0 GHz which is suitable for places where $4{\times}4$ MIMO systems are supposed to be deployed such as in China, EU, Korea and Japan at the band ${\times}$ (3.3 - 3.8GHz. The measured 6-dB impedance bandwidths of the proposed antennas are larger than 700 MHz with isolation between the feeding ports higher than 18 dB [1-2]. The simulation and measurement results show that the proposed antenna concept is a very promising alternative for 5G mobile applications.

• Journal of Electrical Engineering and Technology
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• 제1권1호
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• pp.73-79
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• 2006

Conceptually, mechanical port of an electric machine can be doubled and the concept of dual-mechanical-port (DMP) will then give birth to a new breed of electric machines. In this paper, the various possible structures of DMP electric machine are discussed. Basic modeling and analysis issues related to the DMP electric machine are presented. An exemplary design of DMP machine is given and verified by FEM results. Potential applications and future research work are given to conclude the paper.

• 대한전자공학회논문지SD
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• 제39권3호
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• pp.20-33
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• 2002

현재 다양한 분야에서 이중 포트 메모리의 사용이 증가함에 따라서 이중 포트 메모리의 고장을 진단하기 위한 효율적인 고장 진단 알고리듬의 필_도성이 증대되고 있다. 따라서 본 논문에서는 이중 포트 메모리에서의 효율적인 고장 진단 알고리듬을 제시하여 이중 포트 메모리에서 발생하는 거의 모든 종류의 고장에 대한 진단을 가능하게 한다. 또한 진단 과정에서 착오를 일으키지 않고 다양한 고장 모델을 구별하며 고장과 관련된 위치를 정확하게 확인하는 것이 가능하다. 새로운 진단 알고리듬을 사용함으로서 이중 포트 메모리에서의 고장 진단과정은 효과적으로 수행될 수 있으며 이전의 다른 연구들과의 성능 평가를 통해 효율성을 확인할 수 있다.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제8권5호
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• pp.590-597
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• 2002

휴대폰과 PDA가 결합된 PDA폰에 대한 관심의 증가와 더불어 다양한 종류의 PDA폰이 연구 개발되고 있다. PDA폰은 내부적으로 CDMA 송수신을 담당하는 CDMA 프로세서와 인터넷 애플리케이션을 담당하는 PDA 프로세서가 결합된 구조를 가지고 있다. 일반적으로 두 프로세서가 통신하는데는 UART, 즉 직렬 통신포트가 사용되었다. 하지만 발전하고 있는 CDMA 규격은 곧 IMT-2000의 등장과 함께 최대 2Mbps의 대역폭을 요구하고 있으며 기존의 직렬포트로는 이 규격을 만족하는데 어려움이 있다. 본 논문에서는 앞으로 고속화될 데이타 통신규격을 만족시킬 프로세서간 통신 메커니즘을 분석하고, Dual port Memory와 USB를 가장 유력한 후보로 선정, 이를 실험할 수 있는 테스트보드를 제작하였다. 실험결과 두 방식 모두 요구 대역폭을 만족시키나, Dual Port Memory를 이용한 방식이 가격대 성능비에서 우수하였다.

• ETRI Journal
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• 제32권1호
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• pp.84-92
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• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.533-534
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• 2008

By using Dual Port DRAM to Multi-media SoC, an improved performance is achieved in this paper. The proposed scheme greatly help the multi-media SoC like a application for full HDTV, and it can be extended to the application field which is needed the low access latency with heavy traffic. Additionally, the proposed scheme help to down the BUM cost of system.

• ETRI Journal
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• 제35권5호
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• 방송과미디어
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• 제11권1호
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• pp.78-85
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• 2006

Cognitive radio is a paradigm for wireless communication in which either network of wireless node itself changes particular transmission or reception parameters to execute its tasks efficiently without interfering with the licensed users. This paper represents a performance of the cognitive radio technology on dual polarized MIMO system using six-port receiver. Six-port technology is well known direct conversion receiver. In this paper, a six-port phase discriminator based polarization signal separation is shown. That is, the SER(Symbol Error Rate) performance is improved using polarization separator and simple receiver architecture is proposed applying six-port receiver. The six-port technology has priority to adapt changeable frequency system and variable environments for cognitive radio. In general, dual polarized MIMO system has good capacity and quality using polarization separator [1].

• 대한전자공학회논문지SD
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• 제41권5호
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• pp.115-131
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• 2004

이중 포트 메모리의 사용이 증가함에 따라, 이중 포트 메모리의 테스트와 진단이 중요하게 여겨지고 있다. 본 논문에서는 메모리의 테스트 과정에서 고장이 검출되었을 때, 발생한 고장의 종류를 세부적으로 분류할 수 있는 새로운 진단 알고리듬을 제안한다. 본 알고리듬에서는 진단을 위한 패턴뿐만 아니라 테스트 결과를 통하여 얻을 수 있는 정보를 이용하여 진단 과정의 효율성을 증대하였으며, 이중 포트 메모리에서 발생할 수 있는 다양한 고장에 대하여 진단이 가능하다.

• ETRI Journal
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• 제30권4호
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• pp.555-564
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• 2008

This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.