References
- S. J. Wang, C. J. Wei, 'Efficient built-in self-test algorithm for memory', Proc. Of Asian Test Symposium, pp. 66-70, 2000 https://doi.org/10.1109/ATS.2000.893604
- C. T. Juang, J. R.Huang, 'A programmable built-in self-test core for embedded memories,' Proc. Of Asia and South Pacific Design Automation Conference, pp. 11-12, 2000 https://doi.org/10.1109/ASPDAC.2000.835054
- S. Hamdioui, M. Rodgers, A.J. Van de Goor, D.Eastwick, 'March tests for realistic faults in two-port memories,' Proc. of IEEE International Workshop on Memory Technology, Design and Testing, pp. 73 -78, 2000 https://doi.org/10.1109/MTDT.2000.868618
- C. F. Wu, C. T. Huang, K. L.Cheng, C. W. Wang, C. W. Wu, 'Simulation-based test algorithm generation and port scheduling for multi-port memories.' Proc. of Design Automation Conference, pp. 301 -306, 2001
- P. Nagaraj, S. Upadhyaya, K. Zarrineh, D. Adams, 'Defect analysis and a new fault model for multi-port SRAMs,' Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 366 -374, 2001 https://doi.org/10.1109/DFTVS.2001.966790
- M. F. Chang, W. K. Fuchs and J. H. Patel, 'Diagnosis and repair of memory with coupling faults,' IEEE Trans. on computers, pp. 493-500, 1989 https://doi.org/10.1109/12.21142
- T. J. Bergfeld, D. Niggemeyer and E. M. Rudnick, 'Diagnostic testing of embedded memories using BIST,'Proc. of IEEE Design Automation and Test in Europe Conference and Exhibition, pp. 305-309, 2000 https://doi.org/10.1109/DATE.2000.840288
- C. W. Wang, C. F. Wu, J. F. Li, C. W. Wu, T. Teng , K. Chiu and H. P. Lin 'A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM,' Proc. of the NinthAsian Test Symposium, pp. 45 -50, 2000 https://doi.org/10.1109/ATS.2000.893601
- J. F. Li, K. L. Cheng, C. T. Huang and C. W. Wu, 'March-based RAM diagnosis algorithms for stuck-at and coupling faults,' Proc. of International Test Conference, pp.758 -767, 2001 https://doi.org/10.1109/TEST.2001.966697
- V.A. Vardanian, Y. Zorian, ' A March-based fault location algorithm for static random access memories,' Proc, of IEEE International Workshop on Memory Technology, Design and Testing, pp. 10-12, 2002 https://doi.org/10.1109/MTDT.2002.1029765
- 박한원, 강성호, '이중 포트 메모리를 위한 고장 진단 알고리듬,' 전기학회 논문지 50권 4호, pp. 192-200, 2001
- S. Hamdioui, A. J. van de Goor, 'Thorough testing of any multiport memory with linear tests,' IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 217 -231, 2002 https://doi.org/10.1109/43.980260
- 김지혜, 배상민, 송동섭, 강성호,'March C-에 바탕을 둔 이중 포트 메모리를 위한 테스트 알고리듬,' 제 3회 한국 테스트 학술대회, pp. 140-144, 2002