• Title/Summary/Keyword: dual-port

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A High-Isolation MIMO Antenna with Dual-Port Structure for 5G Mobile Phones

  • Yang, Hyung-kyu;Lee, Won-Woo;Rhee, Byung-Ho
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.4
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    • pp.1458-1470
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    • 2018
  • In this letter, a new dual-port Multiple-Input Multiple-Output (MIMO) antenna is introduced which has two independent signal feeding ports in a single antenna element to achieve smaller antenna volumes for the 5G mobile applications. The dual-port structure is implemented by adding a cross coupled semi-loop (CCSL) antenna as the secondary radiator to the ground short of inverted-F antenna (IFA). It is found that the port to port isolation is not deteriorated when an IFA and CCSL is combined to form a dual-port structure. The isolation property of the proposed antenna is compared with a polarization diversity based dual-port antenna proposed in the literature [9]. The operating frequency range is 3.3-4.0 GHz which is suitable for places where $4{\times}4$ MIMO systems are supposed to be deployed such as in China, EU, Korea and Japan at the band ${\times}$ (3.3 - 3.8GHz. The measured 6-dB impedance bandwidths of the proposed antennas are larger than 700 MHz with isolation between the feeding ports higher than 18 dB [1-2]. The simulation and measurement results show that the proposed antenna concept is a very promising alternative for 5G mobile applications.

A New Breed of Electric Machines - Basic Analysis and Applications of Dual Mechanical Port Electric Machines

  • Xu Longya
    • Journal of Electrical Engineering and Technology
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    • v.1 no.1
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    • pp.73-79
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    • 2006
  • Conceptually, mechanical port of an electric machine can be doubled and the concept of dual-mechanical-port (DMP) will then give birth to a new breed of electric machines. In this paper, the various possible structures of DMP electric machine are discussed. Basic modeling and analysis issues related to the DMP electric machine are presented. An exemplary design of DMP machine is given and verified by FEM results. Potential applications and future research work are given to conclude the paper.

Fault Diagnosis Algorithm for Dual Port Memories (이중 포트 메모리를 위한 고장 진단 알고리듬)

  • Park, Han-Won;Gang, Seong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.3
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    • pp.20-33
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    • 2002
  • As dual port RAMs are widely used in the various applications, the need for an efficient algorithm to diagnose faults in dual port RAMs is increased. In this paper we propose an efficient algorithm that can diagnose all kinds of faults in dual port RAMs. In addition, the new algorithm can distinguish various fault models and locate the position related to each fault. Using the new algorithm, fault diagnosis for dual port RAMs can be performed efficiently and the performance evaluation with previous approaches proves the efficiency of the new algorithm.

Implementation and Performance Analysis of High Speed Communication Mechanism between Internet Processor and CDMA Processor (인터넷 프로세서와 CDMA 송수신 프로세서간의 고속 데이타 전송 메커니즘 구현 및 성능분석)

  • Jung, Hae-Seung;Chung, Sang-Hwa
    • Journal of KIISE:Computing Practices and Letters
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    • v.8 no.5
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    • pp.590-597
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    • 2002
  • Currently, with the increasing demand for combining cellular phone and PDA, various kinds of PDA-phones are being developed. A typical PDA-phone consists of a CDMA processor and a PDA processor. Generally, a UART serial communication port is used for inter-processor communication. However, the CDMA standard will need more data bandwidth over 2Mbps with the emergence of IMT-2000. The bandwidth requirement is beyond the capability of UART. In this paper, several inter-processor communication mechanisms are analyzed and especially Dual Port Memory and USB were chosen as the candidates for the new communication mechanism. A prototype PDA-phone board has been implemented for experiment. The experimental result shows that Dual Port Memory is better than USB in cost performance.

Dual-Port SDRAM Optimization with Semaphore Authority Management Controller

  • Kim, Jae-Hwan;Chong, Jong-Wha
    • ETRI Journal
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    • v.32 no.1
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    • pp.84-92
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    • 2010
  • This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

Performance enhancement using dual port DRAM in Mobile SoC (Mobile SoC에서의 Dual Port DRAM을 사용한 Performance 향상)

  • Roh, Jong-Ho;Chung, Eui-Young
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.533-534
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    • 2008
  • By using Dual Port DRAM to Multi-media SoC, an improved performance is achieved in this paper. The proposed scheme greatly help the multi-media SoC like a application for full HDTV, and it can be extended to the application field which is needed the low access latency with heavy traffic. Additionally, the proposed scheme help to down the BUM cost of system.

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A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory

  • Park, Youngkyu;Kim, Hong-Sik;Choi, Inhyuk;Kang, Sungho
    • ETRI Journal
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    • v.35 no.5
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    • pp.808-818
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    • 2013
  • Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

Performance of Dual Polarized MIMO System using Six-Port Receiver for Cognitive Radio

  • Lee Sang-Yub;Yang Wan-Cheol;Lee Jeong-Suk;Kim Hak-Sun
    • Broadcasting and Media Magazine
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    • v.11 no.1
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    • pp.78-85
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    • 2006
  • Cognitive radio is a paradigm for wireless communication in which either network of wireless node itself changes particular transmission or reception parameters to execute its tasks efficiently without interfering with the licensed users. This paper represents a performance of the cognitive radio technology on dual polarized MIMO system using six-port receiver. Six-port technology is well known direct conversion receiver. In this paper, a six-port phase discriminator based polarization signal separation is shown. That is, the SER(Symbol Error Rate) performance is improved using polarization separator and simple receiver architecture is proposed applying six-port receiver. The six-port technology has priority to adapt changeable frequency system and variable environments for cognitive radio. In general, dual polarized MIMO system has good capacity and quality using polarization separator [1].

An Efficient Test and Diagnosis Algorithm for Dual Port Memories (이중 포트 메모리를 위한 효과적인 테스트와 진단 알고리듬)

  • 김지혜;김홍식;김상욱;강성호
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.115-131
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    • 2004
  • As dual port memories are being frequently used, test and diagnosis for dual port memories becomes more important. In this paper, anew diagnosis algerian which can classify faults in detail when the fault is detected during test process is developed. The new algerian increases its efficiency by using the information that can be obtained by test results as well as results using additional diagnostic pattern set. In addition the algorithm can diagnose various fault models for dual port memories.

An Effective Test and Diagnosis Algorithm for Dual-Port Memories

  • Park, Young-Kyu;Yang, Myung-Hoon;Kim, Yong-Joon;Lee, Dae-Yeal;Kang, Sung-Ho
    • ETRI Journal
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    • v.30 no.4
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    • pp.555-564
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    • 2008
  • This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.

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