• Bulletin of the Korean Space Science Society
• /
• 2003.10a
• /
• pp.63-63
• /
• 2003

There are many actuators and sensors used for attitude control system for KOMPSAT such as Reaction Wheel Assembly, Magnetic Torque Assembly, Dual Thruster Module, Solar array Drive, Three Axis Magnetometer, Conical Earth Sensor, Fine Sun Sensor Assembly, Coarse Sun Sensor Assembly, Gyro Reference Assembly and so on. For KOMPSA T satellite it has been considered using the Magnetic Torquer (MTQ) generating the magnetic dipole moment. In general, the magnetic dipole moment for satellite attitude control system is used for dumping out the excessive reaction wheel momentum so that the reaction wheel speed is not saturated. The objective of this study is to analyze the magnetic field characteristics generated by the Magnetic Torquer using the Maxwell 2D Field Simulator software. Currently, the developing model (DM) of the MTQ is being developed and manufactured at a company under the supervision of KARL MTQ is an electromagnet consisting of a ferromagnetic cylindrical core on which an excitation coil is wound. A current is passed through the coil to produce a dipole momentum in the ferromagnetic core. The configuration of the MTQ will be introduced in the presentation. The 2 dimensional model of the MTQ is drawn as axisymmetric models in RZ plane, and each corresponding material is assigned to the each MTQ object, the core, coil, and background. After the boundary conditions, current sources, and solution parameters are set up, the magnetic field intensities, directions, and other values specified by users can be calculated by using the finite element analysis. The theoretical magnetic field quantities obtained by the Maxwell 2D Simulator can be used for the basis of the development of the MTQ.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.786-792
• /
• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• Proceedings of the Korea Contents Association Conference
• /
• 2009.05a
• /
• pp.17-22
• /
• 2009

DaVinci processors are popular media processors for implementing embedded multimedia applications. They support dual core architecture: ARM9 core for video I/O handling as well as system management and peripheral handling, and DSP C64+ core for effective digital signal processing. In this paper, we propose our efforts for optimal implementation of object tracking algorithm in DaVinci-based smart camera which is being designed and implemented by our laboratory. The smart camera in this paper is supposed to support object detection, object tracking, object classification and detection of intrusion into surveillance regions and sending the detection event to remote clients using IP protocol. Object tracking algorithm is computationally expensive since it needs to process several procedures such as foreground mask extraction, foreground mask correction, connected component labeling, blob region calculation, object prediction, and etc. which require large amount of computation times. Thus, if it is not implemented optimally in Davinci-based processors, one cannot expect real-time performance of the smart camera.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.9
• /
• pp.26-37
• /
• 2016

The core technologies of the current transport network are OAM and protection switching to meet the sub-50ms protection switching time via a path redundancy when a link or node failure occurs. The transport networks owned by public network operators, central/local governments, and major enterprises are individually configured and managed with service resiliency in each own protected sub-network. When such networks are cascaded, it is also important to provide a node resiliency between two protected sub-networks. However, the linear protection switching in packet transport networks, such as MPLS-TP and Carrier Ethernet, does not define a solution of dual node interconnection. Although Ethernet ring protection switching covers the dual node interconnection scheme, a large amount of duplicated data frames may be flooded when a failure occurs on an adjacent (sub) ring. In this paper, we suggest a dual node interconnection scheme with linear protection switching technology in multiple protected sub-networks. And we investigate how various protected sub-network combinations with a proposed linear or ring protection process impact the service resiliency of multiple protected sub-networks through extensive experiments on link and interconnected node failures.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.5B no.3
• /
• pp.248-252
• /
• 2005

This paper deals with a new design method for a small-size rotating machine with high power. In order to achieve high performance, secondary excitation by Nd-Fe-B magnets and the grain oriented electrical steel sheets were selected and a new design using dual rotors is proposed. The outline of the high-performance rotating machine will be presented and the results of the finite element analysis by using this method combined with the E&SS modeling will be shown in the paper.

• Proceedings of the Korean Information Science Society Conference
• /
• 1998.10a
• /
• pp.700-702
• /
• 1998

자바(Java)의 수행 성능을 향상시키기 위한 방법으로 자바 프로세서가 제안되었다. 그러나 현재의 자바 프로세서는 자바 가상 머신(Java Virtual Macjine)의 구조만을 고려한 것이다. 본 논문에서는 기존 자바 프로세서의 성능을 향상시키는 자바 프로그래밍에서 사용되는 다중스레드를 직접 지원하는 새로운 자바 프로세서인 동시 다중스레드 자바 칩(Simultaneous Multithreaded Java Chip SMTJC)을 제안한다. SMTJC은 두 개의 독립적인 스레드를 동시에 수행함으로써, 자바 프로그램에서의 명령어 수준 병렬성(Instruction level parallelism)을 향상시킨다. 다중스레드 수행을 위해 새로운 스택 캐쉬의 구조 및 운영 방법을 사용한다. JavaSim을 통한 시뮬레이션은 SMTJC 이 기존 자바 프로세서에 비해 이중 스택 캐쉬와 추가적 처리 유닛들로 인해 1.28~2.00의 전체적 수행 성능이 향상됨을 보여준다. 본 연구는 하드웨어와 소프트웨어의 상호 보안적인 기술적 경향을 배경으로 자바의 언어적 특성을 고려한 프로세서를 설계, 지원함으로써 자바 프로세서의 성능 향상을 도모하고 있다.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.10 no.4
• /
• pp.233-239
• /
• 2015

This paper describes a method that is integrated trace for real-time virtualization environment. This method has solved the problem that the performance trace may not be able to analyze integrated method between heterogeneous operating systems which is consists of real-time operating systems and general-purpose operating system. In order to solve this problem, we have attempted to reuse the performance analysis function in general-purpose operating system, thereby real-time operating systems can be analyzed along with general-operating system. Furthermore, we have implemented a prototype based on ARM Cortex-A15 dual-core processor. By using this integrated trace method, real-time system developers can be improved productivity and reliability of results on real-time virtualization environment.

• Proceedings of the IEEK Conference
• /
• 2003.07d
• /
• pp.1375-1378
• /
• 2003

다중 프로세서 내장 SoC의 동작 검증에는 많은 연산과 시간을 필요로 한다. 본 논문에서는 듀얼 프로세서 내장 SoC AISC의 검증을 위해 가상 명령어 세트를 기반으로 한 프로그램 소프트웨어 모델(PSM)과 버스 트랜잭션을 발생시키는 프로세서 마크로 엔진 모델(PEM)을 사용한 검증 방법을 제시한다. 제시된 방법은 추상화된 가상 마크로 엔진 명령 세트를 사용함으로써, 적은 컴퓨팅 리소스로 다중프로세서 내장 SoC의 검증을 보다 빠르게 수행할 수 있다.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.64 no.4
• /
• pp.267-272
• /
• 2015

Active noise control (ANC) is a method of cancelling a noise signal in an acoustic cavity by generating an appropriate anti-noise signal via canceling loudspeakers. The continuous progress of ANC involves the development of improved adaptive signal processing algorithms, transducers, and DSP hardware. In this paper, the convergence behavior and the stability of the FxLMS algorithm in ANC systems with real-time implementation is proposed. Specially, The advanced DSP H/W with dual core(DSP+ARM) and API(application programming interface) S/W programming was developed to improve the real-time implementation performance under the FxLMS algorithms of input noise such as road noise environment. The experimental results are found to be in good agreement with the theoretical predictions.

• Journal of Computing Science and Engineering
• /
• v.6 no.4
• /
• pp.267-278
• /
• 2012

The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).