DOI QR코드

DOI QR Code

Design of Encryption/Decryption Core for Block Cipher Camellia

Camellia 블록 암호의 암·복호화기 코어 설계

  • Sonh, Seungil (Department of Information and Telecommunications, Hanshin University)
  • Received : 2016.01.05
  • Accepted : 2016.04.01
  • Published : 2016.04.30

Abstract

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

Camellia 암호는 NTT사 및 미쓰비시 전자회사에서 공동으로 2000년도에 개발되었다. Camellia는 128비트 메시지 블록 크기와 128비트, 192비트 및 256비트 키(Key)에 대한 암호화 방식을 규정하고 있다. 본 논문은 키 스케줄용 레지스터 설정과 기존의 라운드 연산 블록을 통합한 수정된 라운드 연산 블록을 제안하였다. 키 생성과 라운드 연산에 필요한 총 16개의 ROM을 단지 4개의 이중포트 ROM만을 사용하여 구현하였다. 또한 메시지 버퍼를 제공하여 키 생성을 위한 KA와 KB 값이 도출되면 대기 시간없이 즉시 암호화나 복호화가 수행될 수 있도록 하였다. 제안한 Camellia 블록 암호 알고리즘을 Verilgo-HDL을 사용하고 설계하고, Virtex4 디바이스상에 구현하였으며, 최대 동작 주파수는 184.898MHz이다. 128비트 키 모드에서 최대 처리율은 1.183Gbps이며, 192비트 및 256비트 키 모드에서 최대 처리율은 876.5Mbps이다. 본 논문에서 설계된 암호 프로세서는 스마트 카드, 인터넷뱅킹, 전자상거래 및 위성 방송 등과 같은 분야의 보안 모듈로 응용이 가능할 것으로 사료된다.

Keywords

References

  1. Sungjoo Ha and Jongho Lee, "Design of fast encryption/decryption for block cipher ARIA," Institute of korean electrical and electronics engineers, vol. 57 no. 9, pp.1652-1659, Sep. 2008.
  2. Seungil Sonh, "Design of Encryption/Decryption Core for Block Cipher HIGHT," KIEE, vol.16 no. 4, pp.778-784, April 2012.
  3. Seungil Sonh, Byeongyoon Choi and Mingoo Kang, "Technology Trend of Cipher Chips," KSII, vol.1 no.2, pp.1491-1500, Oct. 2001.
  4. Byeongyoon Choi and Jinil Kim, "CPLD Implementation OF SEED Cryptographic Coprocessor," KISPS, vol. 1 no.1-2, pp.177-185, Oct. 2000.
  5. Ashwini M. Deshpande et al., "FPGA Implementation of AES Encryption and Decryption," International Conf. on control, automation, communications and energy conservation, pp.1-6, June 2009.
  6. M. Matsui and S. Moriai, "A Description of the Camellia Encryption Algorithm," Network Working Group Request for Comments: 3713, Apr. 2004.
  7. Kazumaro Aoki, Tetsuya Ichikawa et al., "Camellia: A 128-bit Block Cipher Suitable for Multiple Platforms," Proceedings of the 7th Annual International Workshop on Selected Areas in Cryptography, pp.39-56, 2000.
  8. Huiju Cheng and Howard Heys, "Compact Hardware Implementation of the Block Cipher Camellia with Concurrent Error Detection," Canadian Conference on Electrical and Computer Engineering, pp.1129-1132, Apr. 2007.
  9. Masashi Watanabe, Keisuke Iwai, Hidema Tanaka, and Takakazu Kurokwwa, "FPGA implementation of Ciphers using Schematic to Program Translator(SPT)," Bulletin of Networking, Computing, Systems, and Software, vol.4, no. 1, pp.1-8, Jan. 2015.
  10. Daniel Denning, James Irvine and Malachy Devlin, "A High Throughput Camellia Implementation," Research in Microelectronics and Electronics, vol. 1, pp137-140, July 2005.