• Proceedings of the KIEE Conference
• /
• 2004.07c
• /
• pp.1585-1587
• /
• 2004

이중 에피층 구조를 가지는 SOI(Silicon-On-Insulator) LIGBT(Lateral Insulated Gate Bipolar Transistor)의 에피층 두께 변화에 따른 항복전압 특성을 분석하였다. 제안된 소자는 전하보상효과를 얻기 위해 n/p-epi의 이중 에피층 구조를 사용하였으며, 에피층 전체에 걸쳐서 전류가 흐를 수 있도록 하기 위해 trenched anode구조를 채택하였다. 본 논문에서는 n/p-epi층의 농도를 고정시킨 후 각각의 epi층의 두께를 변화시켜가며 simulation을 수행하였을 때 항복전압의 변화 및 표면과 epi층에서의 전계분포변화를 분석하였다.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.2
• /
• pp.140-145
• /
• 2002

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).

• Proceedings of the KIPE Conference
• /
• 2011.07a
• /
• pp.287-289
• /
• 2011

본 논문은 인피니언 테크놀로지스의 RC-IGBT (Reverse Conducting Isolated Gate Bipolar Transistor)와 SOI 드라이브 IC(Integrated Circuit)를 사용한 DIL(Dual-In-Line) 구조의 저전력 모듈인 CIPOS TM (Control Integrated POwer System) 제품을 소개한다. 이 전력 모듈은 최적의 게이트 구동회로, 트렌치 필드스톱의 RC-IGBT를 사용하여 기존의 IGBT 와 Diode를 사용하는 구조에서 최소화 된 패키지 크기를 사용하여 높은 효율을 구현할 수 있다. 본 논문을 통하여 인버터의 어플리케이션에 적합하게 설계된 전력모듈에 대한 소개와 그 특징 및 시스템 구성을 위한 고려사항에 대하여 기술하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.8
• /
• pp.966-974
• /
• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.

• Journal of the Korean Society of Safety
• /
• v.36 no.2
• /
• pp.10-17
• /
• 2021

This paper presents the robust design of each component used in the development of an induction bolt heating system for dismantling the high-temperature high-pressure casing heating bolts of turbines in power plants. The induction bolt heating system comprises seven assemblies, namely AC breaker, AC filter, inverter, transformer, work coil, cable, and CT/PT. For each of these assemblies, the various failure modes are identified by the failure mode and effects analysis (FMEA) method, and the causes and effects of these failure modes are presented. In addition, the risk priority numbers are deduced for the individual parts. To ensure robust design, the insulated-gate bipolar transistor (IGBT), switched-mode power supply (SMPS), C/T (adjusting current), capacitor, and coupling are selected. The IGBT is changed to a field-effect transistor (FET) to enhance the voltage applied to the induction heating system, and a dual-safety device is added to the SMPS. For C/T (adjusting current), the turns ratio is adjusted to ensure an appropriate amount of induced current. The capacitor is replaced by a product with heat resistance and durability; further, coupling with a water-resistant structure is improved such that the connecting parts are not easily destroyed. The ground connection is chosen for management priority.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.04b
• /
• pp.45-48
• /
• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.