• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.135-135
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• 2009

In this work we compared the electrical characteristic of single gate and dual gate in MIC-TFT. We fabricated p-channel TFTs based on MIC structure. In mobility, dual gate ($61.35cm^2/Vsec$) got a higher value than single gate ($55.96cm^2/Vsec$). In $I_{on}/I_{off}$ dual gate ($6.94{\times}10^6$) got a higher value than single gate ($1.72{\times}10^6$) too. In $I_{off}$, dual gate got a lower value than single gate. Therefore, dual gate is good and less power consumption than single gate.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2001년도 추계종합학술대회
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• pp.234-237
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• 2001

본 논문은 마이크로파 수신기시스템에서 발생되는 이미지성분을 효과적으로 제거하기 위해서 Dual Gate FETs을 이용한 이미지 제거 특성을 분석하였다. Dual Gate를 이용한 이미지 제거능력을 모의 실험한 결과 RF신호에 대한 이미지 제거특성은 -32dBc을 보였으며, Dual Gate FETs믹서의 변환이득은 1.7 dBm, 5GHz 발진주파수는 -117.3 dBc/100KHz 임을 확인하였다.

• 한국전기전자재료학회논문지
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• 제29권11호
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• pp.681-684
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• 2016

This research was carried out experiments of variety IGBTs for industrial inverter and electric vehicle. The devices for this paper were planar gate IGBT, trench gate IGBT and dual gate IGBT and we designed using same design and process parameters. As a result of experiments, the electrical characteristics of planar gate IGBT were 1,459 V of breakdown voltage, 4.04 V of threshold voltage and 4.7 V of on-state voltage drop. And the electrical characteristics of trench gate IGBT were 1,473 V of breakdown voltage, 4.11 V of threshold voltage and 3.17 V of on-state voltage drop. Lastly, the electrical characteristics of dual gate IGBT were 1,467 V of breakdown voltage, 4.14 V of threshold voltage and 3.08V of on-state voltage drop. We almost knew that the trench gate IGBT was superior to dual gate IGBT in terms of breakdown voltage. On the other hand, the dual gate IGBT was better than the trench gate IGBT in terms of on state voltage drop.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.458-466
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• 2012

A Dual metal gate stack cylindrical/ surrounded gate MOSFET (DMGSA CGT/SGT MOSFET) has been proposed and an analytical model has been developed to examine the impact of this structure in suppressing short channel effects and in enhancing the device performance. It is demonstrated that incorporation of gate stack along with dual metal gate architecture results in improvement in short channel immunity. It is also examined that for DMGSA CGT/SGT the minimum surface potential in the channel reduces, resulting increase in electron velocity and thereby improving the carrier transport efficiency. Furthermore, the device has been analyzed at different bias point for both single material gate stack architecture (SMGSA) and dual material gate stack architecture (DMGSA) and found that DMGSA has superior characteristics as compared to SMGSA devices. The analytical results obtained from the proposed model agree well with the simulated results obtained from 3D ATLAS Device simulator.

• Journal of Information Display
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• 제7권3호
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• pp.27-30
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• 2006

This paper presents a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_{2}O_{3}$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_{2}O_{3}$ as both a top gate dielectric and a passivation layer was investigated. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric was changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_{2}O_{3}$ as a top gate dielectric was changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode was changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure was successfully investigated by an analysis of electrostatic potential.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• 전기전자학회논문지
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• 제21권1호
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• pp.1-6
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• 2017

본 논문에서는 플래너 게이트 및 트렌치 게이트의 구조를 동시에 가지고 있는 1200V급 이중 게이트 IGBT 소자를 제안함과 동시에 전기적인 특성을 분석하였으며, 분석된 결과를 가지고 플래너 게이트 및 트렌치 게이트 IGBT 소자의 전기적인 특성과 비교 분석하였다. 이중 게이트 IGBT 소자를 설계하는데 있어 문턱전압 및 온 상태 전압 강하에 영향을 주는 P-베이스 영역에 있어 P-베이스에 깊이는 트렌치 게이트 소자 영역에 영향을 주며, P-베이스에 너비는 플래너 게이트 소자 영역에 영향을 주는 것을 확인할 수 있었다. 본 연구에서 제시한 이중 게이트 IGBT 소자의 전기적인 특성인 항복전압은 1467.04V, 온 전압 강하는 3.08V, 문턱전압은 4.14V의 특성을 나타내고 있다.

• 전기전자학회논문지
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• 제26권3호
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• pp.500-505
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• 2022

본 연구에서는 새로운 구조의 dual gate tri-layer split channel 박막트랜지스터를 제작하였다. 전류 구동 능력을 향상시키기 위해 액티브 층의 양쪽에 게이트를 형성하였고 전하이동도를 증가시키기 위하여 액티브 층에서 채널이 형성되는 구간인 첫번째 층과 세번째 층에 전도성이 높은 ITO 층을 배치하였다. 추가적으로 분할 채널을 이용하여 채널의 series 저항을 낮추면서 분할한 채널의 측면에서도 accumulation을 유도하여 전하이동도를 향상시켰다. 기존의 single gate a-ITGZO 박막트랜지스터가 15 cm²/Vs의 전하이동도를 가지는 반면 dual gate tri-layer split channel 박막트랜지스터는 134 cm²/Vs의 높은 전하이동도를 가졌다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 C
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• pp.2031-2033
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• 2005

poly-Si TFT의 kink 전류를 억제하는 L-shaped dual-gate TFT 구조를 제안하고 이를 제작하였다. 제안된 소자는 채널의 그레인 방향을 일정하게 성장시키는 SLS나 CW laser 결정화 방법을 사용한다. L자 모양의 게이트 구조를 사용하여 서고 다른 전계효과 이동도를 갖는 두 개의 sub-TFT를 구현할 수 있으며, 이러한 sub-TFT간의 특성차이가 kink 전류를 억제시킨다. 직접 제작한 L-shaped dual-gate 구조의 소자가 poly-Si TFT의 kink 전류를 억제하고, 전류포화 영역에서 전류량을 고정시킴으로써 신뢰성이 향상됨을 확인하였다.