JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOl MOSFETs

  • Balamurugan, N.B. (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University) ;
  • Sankaranarayanan, K. (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University) ;
  • John, M.Fathima (Department of Electronics and Communication Engineering, Thiagarajar College of Engineering, Anna University)
  • Published : 2009.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

Keywords

References

  1. J. T. Park, and J. P. Colinge, "Multi-gate SOI MOSFETs: device design guidelines", IEEE Tran-sactions on Electron Devices, vol. 49, no. 12, pp. 2222-2229, 2002 https://doi.org/10.1109/TED.2002.805634
  2. M. J. Kumar, A. A. Orouji, and H. Dhakad, "New Dual-Material Surrounding Gate Nanoscale MOSFET: Analytical Threshold-Voltage mode", IEEE tran¬sactions on Electron Devices, vol. 53, no. 4, pp. 920-923, 2006 https://doi.org/10.1109/TED.2006.870422
  3. T. K. Chiang, M. L. Chen, and H. K. Wang, "A new Two-dimensional model for Dual Material Surrounding Gate (DMSG) MOSFET's", IEEE Conference on Electron Devices and Solid-state Circuits, vol. 20, pp. 597-600, 2007 https://doi.org/10.1109/EDSSC.2007.4450195
  4. N. B.Balamurugan, K. Sankaranarayanan, and M. Suguna, "A New Scaling Theory for the Effective Conducting Path Effect of Dual Material Surrounding Gate Nanoscale MOSFETs", Journal of Semiconductor Technology and Science, vol. 8, no. 1, pp.92-97, 2008 https://doi.org/10.5573/JSTS.2008.8.1.092
  5. D. Flandre, L. F. Ferreira, P. G. A. Jespers, and J. P. Colinge, "Modeling and Applications of Fully Depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits", Solid-State Electronics, vol. 39, no.4, pp. 455-460, 1996 https://doi.org/10.1016/0038-1101(95)00167-0
  6. K. Rajendran and G. S. Samudra, "Modeling of transconductance-to-current ratio ($g_m/I_D$) analysis on double-gate SOI MOSFETs", Journal of Semi-conductor Science and Technology, vol. 15, pp. 139-144, 2000 https://doi.org/10.1088/0268-1242/15/2/311
  7. A. Kranti, Rashmi, S. Haldar, and R. S. Gupta, "Design and Optimization of Vertical Surrounding Gate MOSFETs for Enhanced transconductance-to-current ratio ($g_m/I_{ds}$)", Solid-state Electronics, vol. 47, pp. 153-159, 2003
  8. N. B. Balamurugan, K. Sankaranarayanan, P. Amutha, and M. Fathima John, "An Analytical Modeling of Threshold and Subthreshold Swing on Dual Material Surrounding Gate Nanoscale MOSFETs for high speed Wireless Communication", Journal of Semiconductor Technology and Science, vol. 8, no. 3, pp. 221-226, 2008 https://doi.org/10.5573/JSTS.2008.8.3.221
  9. MEDICI 4.0 User’s Manual, Technological Modeling Associates, Palo Alto, CA, 1997
  10. K. K. Young, "Analysis of Conduction in Fully Depleted SOI MOSFETs", IEEE transactions on Electron Devices, vol. 36, No. 3, pp. 504-506, 1989 https://doi.org/10.1109/16.19960

Cited by

  1. Effect of Ge Mole Fraction on Electrical Parameters of Si1−xGex Source Step-FinFET and its Application as an Inverter pp.1876-9918, 2018, https://doi.org/10.1007/s12633-018-9846-8