• Speech Sciences
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• v.7 no.2
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• pp.225-234
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• 2000

This paper describes the fixed-point DSP implementation of a CELP(Code-excited linear prediction)-based speech coder. The effective realization methodologies to maximize the utilization of the DSP's architectural features, specifically parallel movement and pipelining are also presented together with the implementation results targeted for the ITU-T standard G.723.1 using Motorola DSP56362. The operation of the implemented speech coder is verified using the test vectors offered by the standard as well as using the peripheral interface circuits designed for the coder's real-time operation.

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.37-40
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• 1999

DSP를 이용한 Brushless DC (BLDC) 모터의 초고속 센서리스 제어 기법 및 그 결과가 제시된다. 초고속 BLDC 모터의 센서리스 제어를 위해서 주 제어기로 DSP TMS320C240이 사용되며 제어 기법으로는 Pulse Amplitude Modulation(PAM) 기법이 사용된다. RAM 제어 기법을 사용함으로서 인버터는 six-step 방식으로 구동되며 속도 제어는 인버터 DC 링크 앞 단 쵸퍼의 전압 제어에 의해 이루어진다. 회전자 위치는 역기전력 센싱 방식에 의해 추정되며 TMS320C240의 Event Manager Module에 입력되어 Commutation 위치 및 속도가 계산된다. 계산된 속도는 디지털 PI 제어 알고리즘에 의해 처리되며 제어기의 출력은 쵸퍼의 duty 비를 변화시킨다. 개발된 DSP 제어 보드 및 제어 알고리즘의 성능을 시험하기 위해 실험이 수행되었으며 전체 제어 알고리즘은 DSP TMS320C240의 어셈블리 프로그램에 의해 구현된다. 결과로 최고 속도 50000 [rpm]에서 이상적인 응답 특성을 얻을 수 있었다.

• The Journal of the Acoustical Society of Korea
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• v.25 no.4E
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• pp.137-141
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• 2006

This paper presents HE-AAC decoder optimization on TMS320C55x fixed-point DSP core using a DSP-C like FFR code, which provides fast and flexible porting to a DSP core. Our optimization efforts are focused on methodologies that include general optimization methods of FFR code suitable for general DSP or RISC platform in high-level language and software optimization methods in assembly language level. The implementation result requires 48 MIPS and 135 Kbytes memory space to decode 48 Kbps stereo using real Korean S-DMB data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.246-251
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• 2006

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.1 s.24
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• pp.109-116
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• 2006

This paper presents a real time distance measuring device using a W-band linear frequency modulated continuous wave(FMCW) radar and TMS320C6701 digital signal processor(DSP). We used FFT operation for measuring distance with the beat signals and the results of FFT could be converted to distance with ease. We presented how to implement a real time miniaturized hardware system including network protocols using a single DSP core. Also how to control the modulation signal of FMCW system to compensate the VCO nonlinearity using the Time Gating control of DSP is presented. We have shown that the proposed system has good performances for measuring distance in real time via outdoor environment experiments.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.264-267
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• 2003

The stereoscopic vision robot system design with DSP processor is presented. The vision system is consists of control system, vision system and host computer. The vision system is based on 32bits DSP processor. The stereoscopic image processing applies the correlation coefficient method to execute the software. The result of experiment, image recognition rate is 95% on the stereoscopic vision robot system.

• Speech Sciences
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• v.3
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• pp.177-186
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• 1998

This paper describes the procedure of implementing a real-time speech codec, G.723.1 which was developed by DSP Group and standardized by ITU-T, using fixed-point DSP, ADSP-2181. This codec has two bit rates associated with it, 5.3 and 6.3 kbit/s. We implemented only one bit rate, 6.3 kbit/s, of the two with fixed-point 32-bit precision. According to the result of the experiment, the amount of computational burden is about 55 MIPS and its quality is similar to the result of the PC simulation with floating-point arithmetic. In this paper, we proposed a method to use a fixed-point DSP and a procedure for developing a real-time speech codec using DSPs and finally developed a G.723.l speech codec for ADSP-2181.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.6
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• pp.168-176
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• 1996

A diagnosis system which can monitor tool breakage and chipping in real time was developed using a DSP(Digital Signal Processor) board in face milling operation. AR modelling and band energy method were used to extract the feature of tool states from cutting force signals. Artificial neural network embedded on DSP board discriminates different patterns from features got after signal processing. The features extracted from AR modelling are more accurate for the malfunction of a process than those from band energy method, even though the computing speed of the former is slow. From the processed features, we can construct the real time diagnosis system which monitors malfunction by using a DSP board having a parallel processing capability.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.93-101
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• 2019

This paper presents a software design and implementation of software-defined radio based IEEE 802.11ac encoder using Texas Instruments TMS320C6670 digital signal processor (DSP) platform. In this paper, the implemented encoder has the capability of generating all the signals consisting of preamble field and data field under different modulation & coding scheme in the IEEE 802.11ac standard. Moreover, the flexibility in choosing different rate, bandwidth, or mode can also be achieved by software reconfiguration using the DSP. As a result, by utilizing the computing power provided by multi-cores as well as the FFT coprocessors in the DSP, the required maximum throughput 78Mbps can be fully reached within 4 ㎲ for each OFDM symbol in the case of 20MHz bandwidth of IEEE 802.11ac.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.55-59
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• 2003

In this paper, we estimate the performance requirements of general-purpose DSP for Carrier Recovery of OFDM DVB-T receiver. Firstly, we transported the designed fixed-point OFDM DVB-T model to a floating-point software model written in C. Then, we measured the number of instruction cycles required for operation of Carrier Recovery in time. We use SignalMaster$\^$TM/ DSP platform of LYRtech Inc. as a environment of estimation, and Simulink$\^$TM/ as a graphical interface, Code Composer StudioTM of TI as profiler and compiler, and SPW$\^$TM/ for presenting functional reliability and comparing the performance distortion with fixed-point model. As a result, we show the required number of DSPs in our DSP-based system, and introduce the need of Multi-DSP-based system.