JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Implementation Method of Cycle Accurate Simulator for the Design of a Pipelined DSP

  • Park, Hyeong-Bae (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Park, Ju-Sung (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Kim, Tae-Hoon (Dept. of Electronics Engineering Pusan National Univ.) ;
  • Chi, Hua-Jun (Dept. of Electronics Engineering Pusan National Univ.)
  • Published : 2006.12.31
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Abstract

In this paper, we introduce an implementation method of the CBS (Cycle Base Simulator), which describes the operation of a DSP (Digital Signal Processor) at a pipeline cycle level. The CBS is coded with C++, and is verified by comparing the results from the CBS and HDL simulation of the DSP with the various test vectors and application programs. The CBS shows the data about the internal registers, status flags, data bus, address bus, input and output pin of the DSP, and also the control signals at each pipeline cycle. The developed CBS can be used in evaluating the performance of the target DSP before the RTL(Register Transfer Level) coding as well as a reference for the RTL level design.

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References

  1. P. Bose, T. M. Conte, T. M. Austin, 'Challenges in processor modeling and validation,' Micro, IEEE, Volume 19, Issue 3, pp. 9-14, May-June 1999 https://doi.org/10.1109/MM.1999.768495
  2. A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, A. Hoffmann, 'A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation,' Design Automation Conference 39th, pp. 22-27, June 2002 https://doi.org/10.1145/513918.513927
  3. A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, H. Meyr, 'A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language,' Computer-Aided Design of Integrated Circuits and Systems, pp. 1338-1354, Nov. 2001 https://doi.org/10.1109/43.959863
  4. Guillermo Maturana, James L. Ball, Jeffery Gee, 'Incas: A Cycle Accurate Model of $UltraSPARC^{TM}$,' Computer Design IEEE, pp. 130-135, Oct. 1995 https://doi.org/10.1109/ICCD.1995.528801
  5. Lisa Guerra, Joachim Fitzner, Dipankar Talukdar 'Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification,' Design Automation Conference IEEE, pp. 364-369, June 1999 https://doi.org/10.1145/309847.310107
  6. R. Voith, 'The $PowerPC^{TM}$ 603 C++ $Verilog^{TM}$ Interface Model,' Digest of papers-Spring compCon 94, IEEE Computer Society Press, pp. 337-340, March 1994 https://doi.org/10.1109/CMPCON.1994.282909
  7. Moon Gyung Kim, Byung In Moon, Sang Jun An, 'Implementation of a Cycle-based Simulator for the Design of a Processor Core', AP-ASIC '99 IEEE, pp. 108-111, Aug. 1999 https://doi.org/10.1109/APASIC.1999.824040
  8. Luc Semeria, Abhijit Ghosh, 'Methodology for Hardware/Software Co-verification in C/C++,' Design Automation Conference, pp. 405- 408, Jan. 2000 https://doi.org/10.1145/368434.368712
  9. Mayan Moudgill, 'Techniques for Implementing Fast Processor Simulators,' Simulation Symposium 31st Annual, pp. 83-90, April 1998 https://doi.org/10.1109/SIMSYM.1998.668450
  10. Stuart Sutherland, 'The Verilog PLI handbook : a user's guide and comprehensive reference on the Verilog programming language interface,' Kluwer Academic Publishers, 1993
  11. Mittra Swapnajit, 'Principles of Verilog PLI,' Kluwer Academic Publishers, 1999