• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.229-232
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• 2000

In this study, An active band grass filter for 2.14GHz have been designed with MMIC using negative resistance circuit. The negative resistance element was realized with a common-drain FET with series inductive feedback. The designed active filter showed an insertion loss of 0dB at 2.14GHz and a 3-dB bandwidth of 125MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.1-12
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• 2001

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.534-540
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• 2008

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse, are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of neural networks.

• Proceedings of the Korean Geotechical Society Conference
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• 1999.10a
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• pp.81-86
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• 1999

The installation of vertical drains by means of a mandrel causes significant remolding of the subsoil, especially in the immediate vicinity of the mandrel. Thus, a zone of smear will be developed with reduced permeability and increased compressibility. This paper is mainly concerned with a field study to investigate the effect of smear due to vertical drain installation. In the present study, a field smear test was conducted to assess the extent of the smear zone around the vertical drain. The extent of the smear zone around a vertical drain was evaluated from the CPT results. CPT test was carried out to some distance around the mandrel installation. The test results revealed that a smear zone was estimated to be 3.6~5.3 times of the mandrel diameter.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• ETRI Journal
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• v.34 no.6
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• pp.962-965
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• 2012

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi-superjunction (semi-SJ) trench double-diffused MOSFET (TDMOS). In this new process, the thick single insulation layer ($SiO_2$) of a conventional device is replaced by a multilayered insulator ($SiO_2/SiN_x/TEOS$) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on-resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on-resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on-resistance are 108 V and $1.1m{\Omega}cm^2$, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of IKEEE
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• v.11 no.3
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• pp.95-99
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• 2007

In this study, the electrical characteristics of Symmetric and Asymmetric High Voltage MOSFET(HV-MOSFET) under high temperature were investigated. And, the specific on-resistance, threshold voltage, transconductance, drain current of the HV-MOSFETs were measured over a temperatures range of 300K ${\leq}$ T ${\leq}$400K. From the result of measured data, specific on-resistance increases slightly with increasing temperature. Especially, at high temperature(at 400K) specific on-resistance was increased about 30% than that in room temperature. And, in high temperature condition (at 400K), drain current was decreased about 30%, Also, transconductance(gm) was decreases with increasing temperature.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.72-78
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• 1990

In this paper, the physical meanings of LDD optimization are treated by numerical simulation and related experiments are attempted to analyzed the optimized LDD structure. Firstly, according to the numerical analysis, the electric field under the n-region near drain is low and uniformly distributed and the current flow is widely distributed in this region under the optimized conditions. It is also found that this optimized point should be achieved by globally optimizing all the process and electrical conditions. Secondly, the maximum electric field, which is obtained from the substrate current to the drain current ratio, is minimized under the optimized condition according to the experiment. Further, the device lifetime is maximized and the n-resistance is changed smoothly from the channel resistance to the $n^+$junction resistance.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.546-549
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• 2009

In this paper, we investigated the effects of different source/drain (S/D) electrode materials in thin film transistors (TFTs) based on indium-gallium-zinc oxide (IGZO) semiconductor. A transfer length and effective resistances between S/D electrodes and amorphous IGZO thin-film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low drain voltage. The TFTs fabricated with Cu S/D electrodes showed the lowest contact resistance and transfer length indicating good ohmic characteristics, and good transfer characteristics with a field-effect mobility (${\mu}_{FE}$) of 10.0 $cm^2$/Vs.