• ETRI Journal
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• 제26권6호
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• 대한전자공학회논문지SD
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• 제37권12호
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• pp.1-9
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• 2000

미세구조 N-채널 MOSFET의 게이트-소스 전압에 의존하는 유효 채널 캐리어 이동도와 소스 및 드레인 기생저항의 정확한 분리 추출을 위해서 새로운 ERM-방법을 제안하였다. ERM-방법은 선형영역에서 동작하는 게이트 길이가 다른 두개의 소자($W_m/L_m=30{\mu}m/0.6{\mu}m, 30{\mu}m/1{mu}m$)에 적용되었고 유효 채널 캐리어 이동도를 모델링하고 추출하는 과정에서 게이트-소스 전압에 의존하는 소스 및 드레인 기생저항의 영향을 고려하였다. ERM-방법으로 추출된 특성변수들을 사용한 해석적 모델식과 소자의 측정데이터를 비교해본 결과 오차가 거의 없이 일치하는 것을 확인하였다. 따라서, ERM-방법을 사용하면 대칭구조 및 비대칭구조 소자의 유효 채널 캐리어 이동도, 소스 및 드레인 기생저항과 다른 특성변수들을 정확하고 효율적으로 추출할 수 있을 것으로 기대된다.

• 한국통신학회논문지
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• 제24권10A호
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• pp.1579-1587
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• 1999

게이트 길이가 $0.2\mu\textrm{m}$인 P-HEMT에 대하여 드레인 바이어스 전류의 변화 및 게이트 폭에 대해 스케일링이 가능한 잡음모델을 제안하였다. 본 논문에서는 S-파라미터를 정확히 예측하기 위하여 $\tau$를 제외한 intrinsic 파라미터는 offset를 도입하여 정규화 한 후 스케일링을 하였다. 드레인 포화전류에 대한 드레인 전류의 비율과 게이트 폭을 변수로 하는 소신호 모델 파라미터의 맞춤함수를 구하였다. 또한, 잡음 파라미터를 정확히 예측하기 위하여 진성저항 잡음 온도 $\textrm{T}_{g}$, 게이트 단 전류 잡음원 등가잡음 컨덕턴스 $\textrm{G}_{ni}$, 드레인 단 전류와 게이트 폭에 거의 관계없으며 이의 평균값은 주변온도와 유사한 값으로 $\textrm{G}_{ni}$는 회로 특성에 영향을 미치지 않을 정도로 작은 값으로 추출되었다. 그러므로, $\textrm{G}_{no}$만을 잡음 모델정수로 하는 잡음모델과 $\textrm{T}_{g}$, $\textrm{G}_{ni}$, $\textrm{G}_{no}$를 잡음 모델정수로 하는 잡음모델을 측정값과 비교하여 본 결과 Gno만을 갖는 잡음모델도 측정된 잡음 파라미터와 잘 일치하였다. 따라서, 모델 정수추출이 간단한 $\textrm{G}_{no}$만을 갖는 잡음모델은 게이트 폭과 바이어스 전류에 대해 스케일링이 가능한 실용적인 잡음모델임을 확인하였다.

• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• 한국지반신소재학회논문집
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• 제7권4호
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• pp.37-45
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• 2008

친환경배수재에 대한 현장 적용성을 평가하기 위해 연직배수재와 수평배수재 설치 조합으로 현장시험시공을 수행하였다. 본 시험시공에서는 기존의 천연섬유배수재(FDB)와 새로 개발한 볏짚배수재(SDB) 그리고 플라스틱배수재(PDB)를 연직배수재로 설치하였으며, 화이버매트와 샌드매트를 수평배수재로 사용하였다. 볏짚배수재(SDB) 설치지역을 제외하고는 플라스틱배수재(PDB)와 천연섬유배수재(FDB) 설치 지역에서 측정한 지표침하발생속도와 과잉간극수압 발생/소산 양상은 거의 유사한 것으로 나타났으며, 1차 압밀방치기간동안 측정된 상부 연약층의 콘관입저항력도 설치된 연직배수재 종류와 상관없이 일정하게 증가한 것으로 나타나 천연섬유배수재가 기존의 플라스틱이나 모래재료를 대체할 수 있을 것으로 판단된다.

• 대한전자공학회논문지SD
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• 제42권1호
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• pp.25-32
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• 2005

본 논문에서는 단 채널 GaAs MESFET과 SOI-구조의 Si JFET가 갖는 전형적인 특성: i) 드레인 전압 인가에 의한 문턱전압 roll-off, ii) 포화영역에서의 유한한 ac 출력저항, iii) 채널길이에 대한 드레인 포화전류의 의존성 약화, 등을 통합적으로 기술할 수 있는 해석적 모델을 제안하였다. 채널 방향의 전계 변화를 포함하는 새로운 형태의 가정을 기존의 GCA와 대체하고, 채널의 전류 연속성과 전계-의존 이동도를 고려하여, 공핍영역과 전도 채널에서 2차원 전위분포 식을 도출해 내었다. 이 결과, 문턱전압, 드레인 전류의 표현 식들이 동작전압전 구간의 영역에 걸쳐 비교적 정확하게 도출되었다. 또한 본 모델은 기존의 채널 shortening 모델에 비해 Early 효과에 대한 보다 더 적절한 설명을 제공하고 있음을 보이고 있다.

• 전자공학회논문지A
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• 제33A권10호
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• pp.123-129
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• 1996

LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35$\mu$m CMOS technolgoy. For the fabricated devices we have measured I$_{ds}$-V$_{gs}$ characteristics and compare them to the modeling resutls. First of all, we calculated channel and LDD region mobility from I$_{ds}$-V$_{gs}$ characteristics of 1050$\AA$ sidewall, 5$\mu$m channel length LDD NMOSFET. Then we MOSFET and found good agreement with experiments. Next, we use calculated channel and LDD region mobility to model I$_{ds}$-V$_{gs}$ characteristics of LDD mMOSFET with 1400 and 1750$\AA$ sidewall and 5$\mu$m channel length and obtained good agreement with experiment. The single source/drain device characteristic modeling results indicates that the cahnnel mobility obtained form our model in LDD device is accurate. In the meantime, we found that the LDD region mobility is governed by phonon and surface roughness scattering from electric field dependence of the mobility. The proposed model is useful in device and circuit simulation because it can model LDD device successfully even though it is mathematically simple.

• 한국전기전자재료학회논문지
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• 제21권9호
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• pp.835-843
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• 2008

We have fabricated the source-drain electrodes for OTFTs by screen printing method and manufactured Ag pastes as conductive paste. To obtain excellent conductivity and screen-printability of Ag pastes, the dispersion characteristics of Ag pastes prepared from two types of acryl resins with different molecular structures and Ag powder treated with caprylic acid, triethanol amine and dodecane thiol as surfactant respectively were investigated. The Ag pastes containing Ag powder treated with dodecane thiol having thiol as anchor group or AA4123 with carboxyl group(COOH) of hydrophilic group as binder resin exhibited excellent dispersity. But, Ag pastes(CA-41, TA-41, DT-41) prepared from AA4123 fabricated the insulating layer since the strong interaction between surface of Ag powder and carboxyl group(COOH) of AA4123 interfered with the formation of conduction path among Ag powders. The viscosity behavior of Ag pastes exhibited shear-thinning flow in the high shear rate range and the pastes with bad dispersion characteristic demonstrated higher shear-thinning index than those with good dispersity due to the weak flocculated network structure. The output curve of OTFT device with a channel length of 107 ${\mu}m$ using screen-printed S-D electrodes from DT-30 showed good saturation behavior and no significant contact resistance. And this device exhibited a saturation mobility of $4.0{\times}10^{-3}$ $cm^2/Vs$, on/off current ratio of about $10^5$ and a threshold voltage of about 0.7 V.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• Geomechanics and Engineering
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• 제7권5호
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• pp.525-537
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• 2014

The typical design of ground improvement with prefabricated vertical drains (PVD) and surcharge preloading involves a series of deterministic analyses using averaged or mean soil properties for the various combination of the PVD spacing and surcharge preloading height that would meet the criteria for minimum consolidation time and required degree of consolidation. The optimum design combination is then selected in which the total cost of ground improvement is a minimum. Considering the variability and uncertainties of the soil consolidation parameters, as well as considering the effects of soil disturbance (smear zone) and drain resistance in the analysis, this study presents a stochastic cost optimization of ground improvement with PVD and surcharge preloading. Direct Monte Carlo (MC) simulation and importance sampling (IS) technique is used in the stochastic analysis by limiting the sampled random soil parameters within the range from a minimum to maximum value while considering their statistical distribution. The method has been verified in a case study of PVD improved ground with preloading, in which average results of the stochastic analysis showed a good agreement with field monitoring data.