• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.83-88
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• 2002

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.66-77
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• 2010

Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.19-22
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• 2003

In this paper, a new small size Lateral Trench Electrode Power MOSFET with local doping is proposed. This new structure is based on the conventional lateral power MOSFET. The entire electrodes of proposed device are placed in trench oxide. The forward blocking voltage of the proposed device is improved by 3.3 times with that of the conventional lateral power MOSFET. The forward blocking voltage of proposed device is about 500V. At the same size, a increase of the forward blocking voltage of about 3.3 times relative to the conventional lateral power MOSFET is observed by using TMA-MEDICI which is used for analyzing device characteristics. Because the electrodes of the proposed device are formed in trench oxide respectively, the electric field in the device are crowded to trench oxide. And because of the structure which has a narrow drain doping width, the punch through breakdown can be occurred in higher voltage than that of conventional lateral power MOSFET. We observed that the characteristics of the proposed device was improved by using TMA-MEDICI and that the fabrication of the proposed device is possible by using TMA-TSUPREM4.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Journal of the Korea Institute of Building Construction
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• v.1 no.2
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• pp.185-190
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• 2001

The purpose of this study is the development of practical Dry floor tile unit method that settle the defect of a wet method and designed for resin mat. With use of PE resin which is confirmed the basic property, it is developed that resin mat, joint-sealing compound with fixed form and space management to Dry floor tile unit method. The result of this study is below. 1) To acquire above the 4kgf/$\textrm{cm}^2$ - construction specification criterion, the bonding space that between resin mat and tile has to occupy the 50% of resin mat module space(10,000$\textrm{cm}^2$). 2) Criteria of bonding part plane is below. simpleness of metal form. productivity, uniform quality after injection molding cooling, easy cutting for remain space management, adhesive property, construction ability, transformation of a severed piece under pressure and so on. 3) To get the shape that could protect the interfacial breakdown, it is designed that resin mat and tile are unified after the bond input. 4) Adapted joint-sealing compound is the material of urethane kinds wedge form. Resin mat has the water passageway that could drain the water. 5) To manage the severed piece of tile, the resin mat is likely to divide the half and the quarter and the plastic drainage is developed in the severed piece.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.305-308
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• 2004

We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.67-78
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• 1984

EAROM device is an n-channel MOS transistor with a control gate stack ed on the floating gate. On account of channel injection type, channel lengths are designed 4-8 $\mu$m and chinnel widths 5-14 $\mu$m. These devices which have fourstructures of different type control gate are designed by NMOS 5 $\mu$m design rule and fabricated by double polysilicon gate NMOS Process. Double ion implantation is applied to increase punchthrough voltage and gate-controlled channel breakdown voltage. The drain and gate voltage for programming was 13-17V and 20-25V, respectively. EPROM cell fabricated could be erased not by optical method but by electrical method. The result of charge retention test showed decrease in stored charges by 4% after 200 hours at 1$25^{\circ}C$.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.85-90
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• 2002

$RuO_2$/GaN and related contacts were investigated for Schottky contacts in GaN-Based optical and electronic devices. We demonstrated that an $RuO_2$ film forms a stable Schottky contact on a GaN layer with a barrier height (${\Phi}_B$) of 1.46 eV and transmittance of 70% in the visible and near UV region. $RuO_2$/GaN Schottky diode showed a breakdown at over -50V and leakage current of only 0.3 nA at -5V. The $RuO_2$/GaN Schottky type photodetector had the UV/Visible rejection ratio of over $10^5$ and the responsivity of 0.23 A/W at 330 nm. The $RuO_2$ gate AlGaN/GaN EFET exhibited high drain current ($I_d$) of 689.3 mA/mm and high transconductance ($g_m$) of 197.4 mS/mm. Cut-Off frequency ($f_t$) and maximum operating frequency ($f_{max}$) were measured as 27.0 GHz and 45.5 GHz, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.537-541
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• 2003

The a-Si:H TFTs using ferroelectric of SrTiO$_3$, as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric is better than SiO$_2$, SiN. Ferroelectric increases ON-current, decreases threshold voltage of TFT and also breakdown characteristics. The a-Si:H deposited by PECVD shows absorption band peaks at wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / and 876 $cm^{-1}$ / according to FTIR measurement. Wavenumber 2,000 $cm^{-1}$ /, 635 $cm^{-1}$ / are caused by stretching and rocking mode SiH1. The wavenumber of weaker band, 876 $cm^{-1}$ / is due to SiH$_2$ vibration mode. The a-SiN:H has optical bandgap of 2.61 eV, refractive index of 1.8 - 2.0 and resistivity of 10$^{11}$ - 10$^{15}$ aim respectively. Insulating characteristics of ferroelectric is excellent because dielectric constant of ferroelectric is about 60 - 100 and breakdown strength is over 1 MV/cm. TFT using ferroelectric has channel length of 8 - 20 $\mu$m and channel width of 80 - 200 $\mu$m. And it shows drain current of 3 $\mu$A at 20 gate voltages, Ion/Ioff ratio of 10$^{5}$ - 10$^{6}$ and Vth of 4 - 5 volts.