• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.29-34
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• 1993

In this paper, we used one-dimensional process simulator, SUPREM-II, and two-dimensional device simulator, MINIMOS 4.0 to extract optimal process parameter that can minimize degradation of device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derieved the relationship between process parameter and device characteristics. Here we have presented a method to extract process parameters from design trend curve(DTC) obtained by process and device simulations. We parameters to verify the validity of the DTC method. The experimental result of 0.8 $\mu\textrm{m}$ channel length devices that have been fabricated with optimal that reduces short channel effects, that is, good drain current-voltage characteristics, low body effects and threshold voltage of 1.0 V, high punchthrough and breakdown voltage of 12 V, low subthreshold swing(S.S) values of 105 mV/decade.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.217-220
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• 2002

In this paper, we have investigated electronical chara-cteristics of power LDMOSFETS having different ex-tended gate lengths(1.B${\mu}{\textrm}{m}$, 2.4${\mu}{\textrm}{m}$, 3.O${\mu}{\textrm}{m}$) in the temperature range of 300k-500K. The results of this study indicate that on-resistance, breakdown voltage increase with temperature. and drain current, threshold voltage, transconductance decrease with temperature. Particular the facts, we observed that Le is the more increase, on-resistance is the more decrease. because every conditions are fixed normal states, only change the Le. As a result, Ron/BV, known for a figure of merit of power device, increase with temperature.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1077-1080
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• 2003

This paper show the measured result of electrical characteristics of SOI-LDMOSFET that is one of the high voltage devises. Especially, we observed changes of breakdown voltage, threshold voltage, on-resistance, drain current, and transconductance in accordance with drift length, main parameter of LDMOSFET. Also, we achieved reliability analysis about device operation in high temperature environment because LDMOS is applied to smart power IC.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.683-686
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• 2003

In this paper, we have investigated electrical characteristics of TRENCH GATE POWER MOSFET in the temperature range of 300K to 500K. The results of this study indicate that on-resistance and breakdown voltage increase with the temperature ,but drain current, threshold voltage and transconductance decrease with the temperature. Especially, it is observed that electrical characteristics are improved as numerical unit cells are increased.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.201-204
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• 2001

LDMOSFET devices operated at low temperature have applications on satellite, space shuttle and low temperature system, etc. In this study, we measured the electrical characteristics of 100v Class LDMOSFET for low temperature application. Measurement data are taken over a wide range of temperatures (100K-300K) and various drift region lengths(6.6${\mu}{\textrm}{m}$, 8.4${\mu}{\textrm}{m}$, 12.6${\mu}{\textrm}{m}$). Maximum transconductance, $g_{m}$ and drain current at low temperatures(~100K) increased over about 260%, 50% respectively, in comparison with the data at room temperature. Breakdown voltage B $V_{ds}$, and specific on- resistance decreased. Besides, ratio $R_{on}$ BV, a figure of merit of the device, decreased with decreasing temperature.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.66-73
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• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.

• 전자공학회논문지A
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• 제31A권6호
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• pp.107-116
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• 1994

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• 한국전기전자재료학회논문지
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• 제27권8호
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.