증착시 도핑된 비정질 Si 게이트를 갖는 MOS 캐패시터와 트랜지스터의 전기적 특성

Electrical Properties of MOS Capacitors and Transistors with in-situ doped Amorphous Si Gate

  • 이상돈 (연세대학교 전자공학과) ;
  • 이현창 (연세대학교 전자공학과) ;
  • 김재성 (금성 일렉트론㈜ 중앙연구소 8연구실) ;
  • 김봉렬 (연세대학교 전자공학과)
  • 발행 : 1994.06.01

초록

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

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