• 한국전기전자재료학회논문지
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• 제32권3호
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.170-173
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• 2003

In this paper, we proposed a new bulk LDMOS structure which can be used for RF application, and its fabrication steps were introduced. The simulated devices consist of three types: Bulk device, SLB(SOI Like Bulk), and SOI device. As a result of process and device simulation, we showed electrical characteristics, such as threshold voltage, subthreshold slope, DIBL(Drain Induced Barrier Lowering), off-state current, and breakdown voltage. In this simulation study, the lattice temperature model was adopted to see the device characteristics with lattice temperature during the operation. SLB device structure showed the best breakdown characteristics among the other structures. The breakdown voltage of SLB structure is about 9V, that of bulk is 7V, and that of SOI is 8V.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.

• 전자공학회논문지A
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• 제31A권10호
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• pp.71-78
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• 1994

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

• 전자공학회논문지A
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• 제29A권2호
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 전자공학회논문지A
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• 제30A권12호
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• ETRI Journal
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• 제8권4호
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• pp.103-109
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• 1986

LDD(Lightly Doped Drain) 방식에 의한 MOSFET의 제조 공정 및 특성에 관하여 실험 분석하였다. MOS 소자의 채널 길이가 짧아짐에 따라 드레인 가장자리에서 자체 형성되는 높은 전계로 말미암아 애벌런치 항복 전압(avalanche breakdown voltage)이 상당히 감소 한다. 이 전압을 높여 주기 위한 기술로서 LDD 방식이 적용되었으며 종래의 제조방식에 의한 MOSFET와 비교 기술되었다.

• 한국진공학회지
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• 제11권4호
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• pp.212-217
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• 2002

고신뢰성 트렌치 게이트 MOSFET을 제작하기 위해 트렌치 코너를 pull-back 공정과 수소 열처리 공정을 이용하여 트렌치 코너를 둥글게 만드는 기술을 개발하였고 이를 이용하여 균일한 트렌치 게이트 산화막을 성장시킬수 있었다. 그 결과 수소 열처리 하기 전에 항복전압이 29 V인 것이 수소 열처리한 후 약 36 V로 증가하여 항복 전압에서 약 25% 향상되었다. 그리고 트렌치 게이트를 이용한 MOSFET에서 트렌치 셀이 약 45,000개 일때 게이트와 소스에 10 V를 인가했을 때, 드레인 전류는 약 45.3 A를 얻었고, 게이트 전압의 10 V, 전류를 5 A를 인가한 상태에서 On-저항은 약 55 m$\Omega$ 얻었다.

• Journal of information and communication convergence engineering
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• 제2권2호
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• pp.93-96
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• 2004

The a-Si:H TFT using ferroelectric of $SrTiO_3$ as a gate insulator is fabricated on glass. Dielectric characteristics of ferroelectric are superior to $SiO_2$ and $Si_{3}N_{4}$. Ferroelectric increases on-current, decreases threshold voltage of TFT and also improves breakdown characteristics. The a-SiN:H has optical band gap of 2.61 eV, retractive index of 1.8∼2.0 and resistivity of $10^{13}$~$10^{15}$ $\Omega$cm, respectively. Insulating characteristics of ferroelectrics are excellent because dielectric constant of ferroelectric is about 60∼100 and breakdown strength is over 1MV/cm. TFT using ferroelectric has channel length of 8∼20 $\mu\textrm{m}$ and channel width of 80∼200 $\mu\textrm{m}$. And it shows that drain current is 3.4$\mu\textrm{A}$ at 20 gate voltage, $I_{on}$/$I_{off}$ is a ratio of $10^5$~$10^8$ and $V_{th}$ is 4∼5 volts, respectively. In the case of TFT without ferroelectric, it indicates that the drain current is 1.5 $\mu\textrm{A}$ at 20 gate voltage and $V_{th}$ is 5∼6 volts. With the improvement of the ferroelectric thin film properties, the performance of TFT using this ferroelectric has advanced as a gate insulator fabrication technology is realized.

• ETRI Journal
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• 제24권4호
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• pp.328-331
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• 2002

We investigated the electrical characteristics of p-channel double-diffused MOSFETs (p-LDMOSFETs) with an uneven racetrack source (URS) and a conventional racetrack source (CRS) for PDP driver IC applications. The breakdown voltage of the p-LDMOSFET with the URS in offstate was nearly the same as the p-LDMOSFET with the CRS. However, the breakdown voltage of the p-LDMOSFET with the URS in on-state was about 30% higher than that of the p-LDMOSFET with the CRS, while the saturated drain current of the p-LDMOSFET with the URS was only about 4% lower than that of the p-LDMOSFET with the CRS.