• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.263-269
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• 1996

A comprehensive scaling method is proposed for a scaled-down facility simulating SBLOCA in the CARR passive reactor (CP-1300). The present method consists of two stages: scaling methodology, and validation of scaling methodology and code. The present scaling methodology is based on the integral response scaling method. Through sensitivity study, the condensation of the top of the CMT is identified as one of the little-known phenomenon with high importance which should be addressed for the applicability of the code. Using the similarity of the derived scaling parameters, the major component geometries of the scaled-down facility are determined. In the case of 1/4 height and 1/100 area ratio scaling, it is found out that the power ratio is the same as the area ratio, and the present scaling methodology generates the design parameters of the scaled-down facility without any distortion.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• Nuclear Engineering and Technology
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• v.53 no.3
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• pp.793-803
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• 2021

The small PWR has been paid more and more attention due to its diversity of application and flexibility in the site selection. However, the large core power density, the small containment space and the rapid accident progress characteristics make it difficult to control the containment pressure like the traditional PWR during the LOCA. The pressure suppression system has been used by the BWR since the early design, which is a suitable technique that can be applied to the small PWR. Since the configuration and operating conditions are different from the BWR, the pressure suppression system should be redesigned for the small PWR. Conducting the experiments on the scale down test facility is a good choice to reproduce the prototypical phenomena in the test facility, which is both economical and reasonable. A systematic scaling method referring to the H2TS method was proposed to determine the geometrical and thermohydraulic parameters of the pressure suppression containment response test facility for the small PWR conceptual design. The containment and the pressure suppression system related thermohydraulic phenomena were analyzed with top-down and bottom-up scaling methods. A set of the scaling criteria were obtained, through which the main parameters of the test facility can be determined.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.261-263
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• 2002

CMOS devices have scaled down to sub-50nm gate to achieve high performance and high integration density. Key challenges with the device scaling are non-scalable threshold voltage( $V^{th}$ ), high electric field, parasitic source/drain resistance, and $V^{th}$ variation by random dopant distribution. To solve scale-down problem of conventional structure, a new structure was proposed. In this paper, we have investigated double-gate MOSFET structure, which has the main-gate and the side-gates, to solve these problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• Journal of Korean Society for Geospatial Information Science
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• v.19 no.2
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• pp.19-27
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• 2011

The objective of this study was to suggest technical approaches for preparation and down scaling of climate data used for predicting the potential forest distribution. To predict the forest distribution, we employed a Korean-specific forest distribution model, so-called the TAG(Thermal Analogy Group), and defined the PFT(Plant Functional Types) based on the HyTAG(Hydrological and Thermal Analogy Group). The climate data with 20km spatial resolution were interpolated to fit on the input data format with 1km spatial resolution. Two potential forest distribution maps were estimated using climate data constructed by kriging, one of the interpolation and down-scaling approaches, with and without lapse rate considered. Through the verification process by comparing two potential maps with the actual vegetation map, the forest distribution using the lapse rate was proven to be 38% more accurate.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.361-366
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• 2023

Apache Hadoop, a representative framework for distributed processing of big data, has the advantage of increasing cluster size up to thousands of nodes to improve parallel distributed processing performance. However, reducing the size of the cluster is limited to the extent of permanently decommissioning nodes with defects or degraded performance, so there are limitations to operate multiple nodes flexibly in small clusters. In this paper, we discuss the problems that occur when removing nodes from the Hadoop cluster and propose a dynamic down-scaling technique to manage the distributed cluster more flexibly. To do this, we design and implement a modified Hadoop system and interfaces to support dynamic down-scaling of the cluster which supports temporary pause of a node and reconnection of it when necessary, rather than decommissioning the node when removing a node from the Hadoop cluster. We have verified that effective downsizing can be performed without performance degradation based on experimental results.

• Journal of Information Display
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• v.7 no.3
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• pp.9-12
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.9 s.252
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• pp.825-833
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• 2006

To investigate the moderator coolability for CANDU-6 reactors, a test facility (HU-KINS) has been manufactured as a 1/8 scaled-down of a calandria tank. In the design of the test facility, a scaling law was developed in such a way to consider the thermal-hydraulic characteristics of a CANDU-6 moderator. The proposed scaling law takes into consideration of the energy conservation, the dynamic similitude such as dimensionless numbers, Archimedes number (Ar) and Reynolds number (Re), and thermal-hydraulic properties similitude. Using this proposed scaling law, the thermal-hydraulic scaling analyses of similar test facilities such as the SPEL (1/10 scale) and the STERN (1/4 scale), have been identified. As a result, in the case of the SPEL, while the energy conservation is well defined, the similarities of Ar and the heat density are not well considered. As for the similarity of the STERN, while both the energy conservation and the characteristics of Ar are well defined, the heat density is not. In the meanwhile, the HU-KINS test facility with 1/8 length scaled-down is well similitude in compliance with all similarities of the energy conservation, the fluid dynamics and thermal-hydraulic properties. To verify the adequacy of the similarities in terms of thermal-hydraulics, a computational fluid dynamic (CFD) analysis has been conducted using the CFX-5 code. As the results of the CFD analyses, the predicted flow patterns and variation of axial properties inside the calandria tank are well consistant with those of previous studies performed with FLUENT and this implies that the present scaling method is acceptable.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.494-497
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• 2002

In this paper, we have presented the simulation results about threshold voltage of nano scale lightly doped drain (LDD) MOSFET with halo doping profile. Device size is scaled down from 100nm to 40nm using generalized scaling. We have investigated the threshold voltage for constant field scaling and constant voltage scaling using the Van Dort Quantum Correction Model(QM) and direct tunneling current for each gate oxide thickness. We know that threshold voltage is decreasing in the constant field scaling and increasing in the constant voltage scaling when gate length is reducing, and direct tunneling current is increasing when gate oxide thickness is reducing. To minimize the roll-off characteristics for threshold voltage of MOSFET with decreasing channel length, we know u value must be nearly 1 in the generalized scaling.