• Title/Summary/Keyword: double capacitor

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Performance of Passive Boost Switched Reluctance Converter for Single-phase Switched Reluctance Motor

  • Ahn, Jin-Woo;Lee, Dong-Hee
    • Journal of Electrical Engineering and Technology
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    • v.6 no.4
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    • pp.505-512
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    • 2011
  • A novel passive boost power converter forsingle-phaseswitched reluctance motor is presented. A simple passive circuit is proposed comprisingthree diodes and one capacitor. The passive circuitis added in the front-end of a conventional asymmetric converter to obtain high negative bias. Based on this passive network, the terminal voltage of the converter side is a general DC-link voltage level in parallel mode up to a double DC-link voltage level in series mode. Thus,it can suppress the negative torque generation from the tail current and improve the output power. The results of the comparative simulation and experiments forthe conventional and proposed converter verify the performance of the proposed converter.

Design of Active Regenerative Bidirectional DC-DC Converter Using Electric Railway Simulator (철도차량 시뮬레이터를 이용한 능동회생 양방향 DC-DC 컨버터 설계)

  • Park, Chan-Heung;Kim, Jong-Yoon;Cho, Ki-Hyun;Jang, Su-Jin;Lee, Byoung-Kuk;Won, Chung-Yuen
    • Proceedings of the KIPE Conference
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    • 2007.11a
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    • pp.166-168
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    • 2007
  • 본 논문에서는 직류 지하철 급전시스템에서 발생하는 회생전력을 활용하기 위한 회생전력 제어용 양방향 DC-DC 컨버터 및 EDLC(Electric Double Layer Capacitor)를 이용한 양방향 DC-DC 컨버터의 효율적 충 방전 제어 알고리즘을 제안하였다. 가선전압의 변화에 따른 제어 방법을 제안함으로서 회생전력의 발생으로 인한 가선전압의 상승을 안정적으로 제어할 수 있도록 하였고, 실측된 가선전압과 동일한 직류 급전시스템의 모의가 가능한 가선전압 모의장치를 사용하여 철도차량용 양방향 DC-DC 컨버터의 효율성을 검증하였다.

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A Study on the Energy Storage Mass of Urban Transit System (도시철도시스템의 에너지 저장방식에 관한 연구)

  • Lee, Han-Min;Kim, Gil-Dong;Lee, Chang-Mu
    • 한국신재생에너지학회:학술대회논문집
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    • 2007.06a
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    • pp.831-835
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    • 2007
  • Energy Saving is one of worldwide emerging issues. These days, applicable techniques of railway vehicle's regenerative energy are investigating in worldwide railway industries. Energy saving methods are "Downsizing energy loss" and "Re-utilizing kinetic energy". Useful plans for Downsizing energy loss are "adjusting operation table" and "optimizing running pattern". Furthermore, regenerative energy that is produced with decreasing speed and stoping, is an important element with reducing vehicle's weight, raising equipment 's efficiency, decreasing running resistance and re-configurating running pattern. Sustainable energy storage mass : Flywheel, EDLC(electrical double layer capacitor) and Secondary battery are applied in overseas, but these cases are not reported within the country. This research is reported for problems and economical validity that comes from by installing sustainable regenerative energy storage system in korean railway industries.

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Study of the Reaction between the Dielectric and the Electrode during the Manufacturing of the Ceramic Capaciitor (요업콘덴사 제조에 있어서의 과전체와 전기물질간의 반응검사)

  • 김기호
    • Journal of the Korean Ceramic Society
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    • v.21 no.1
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    • pp.60-66
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    • 1984
  • During the metallization in the manufacturing of the ceramic capacitor at the boundary layer between Pd or Pt electrode and $BaTiO_3$-dielectric reactions were analysed. For the study of the reaction Electron Spin Resonance (ESR) Method was used. With the aid of ESR an increased of the concentration of the paramagnetic $Ti^{3+}$-Centers on the metallizing process could be seen. It meaned a reduction effect although the metallization was accomplished under oxidation atmosphere. Therefore it could be regarded as a reaction at the boundary layer. In order to investigate the reaction ad double octahedral model was compared and the increase of the $Ti^{3+}$-concentration was studied.

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A Design of CMOS ADC for Video Interface (비디오 신호 인터페이스를 위한 CMOS ADC의 설계)

  • 안승헌;권오준;임진업;최중호
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.975-978
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    • 2003
  • 본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.

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Compact Metamaterial-Based Tunable Zeroth-Order Resonant Antenna with Chip Variable Capacitor

  • Jung, Youn-Kwon;Lee, Bomson
    • Journal of electromagnetic engineering and science
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    • v.13 no.3
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    • pp.189-191
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    • 2013
  • This letter presents a compact metamaterial-based tunable zeroth-order resonant antenna. It is based on the double-negative unit cell with a function of tunable inductance realized by a varactor and impedance convertor in the shunt branch. The resonant frequency of the designed antenna ranges from 2.31 to 3.08 GHz, depending on the capacitance of the used varactor. Its size is very compact ($0.05{\lambda}_0{\times}0.2{\lambda}_0$) with a relatively wide tunable range of 29.1%. The impedance bandwidth of the antenna is from 20 to 50 MHz for the resonant center frequency. The measured maximum total realized gain is from -0.68 dBi (2.43 GHz) to 1.69 dBi (2.97 GHz). The EM-simulated and measured results are in good agreement.

Design of a high speed 3rd order sigma-delta modulator (3.3V 고속 CMOS 3차 시그마 델타 변조기 설계)

  • 박준한;윤광섭
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.982-985
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    • 1999
  • An efficient technique to trade off speed for resolution is the sigma-delta modulation (SDM). This paper proposes a new SDM architecture to improve conversion rates and SNR(Signal-to Noise Ratio) by using master clock and four divided clock. The charateristics of the proposed SDM are simulated in MATLAB environment. and optimizing the capacitor sizes is done by iterative processing. other analog characteristics are simulated using 0.65${\mu}{\textrm}{m}$ n-well CMOS process, double poly and single metal. The result of simulation shows that more increasing the effective bits of internal ADC/DAC, bigger the improvement of SNR.

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Analysis of the Unbalance of DC Link Voltage in 12-step Inverter with 2-Phase Chopper Preregulator (2상 쵸퍼 Preregulator를 갖는 12-step 인버터에서의 DC Link단 전압 불평형 해석)

  • Nho, Eui-Cheol;Kim, In-Dong
    • Proceedings of the KIEE Conference
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    • 1995.11a
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    • pp.258-260
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    • 1995
  • This paper deals with the voltage unbalance of DC link voltage in series connected two 6-step inverters with double chopper preregulator. Each output of the 6-step inverter is connected to each transformer. The secondary windings of one of the transformers is zig-zag connected and the other star connected. The secondary terminals of the two transformers are series connected which makes 12-step output voltage waveform. In this case, the characteristics of the two transformers are rather different each other. The difference results in the voltage unbalance of the two 6-step inverter input capacitor voltages which make the DC link voltage. The degree of the voltage unbalance is analysied with the variations of load power, load power factor and % impedance of the transformer.

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Charge Distribution in a capacitor observed by PEA Method (PEA법에 의한 캐패시터내 전하분포 측정)

  • Endrowednes, Kuantama;Han, Deok-Woo;Kwak, Dong-Joo;Sung, Youl-Moon
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.1156-1157
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    • 2008
  • The use of the pulsed electro acoustic (PEA) method allowed us to perform the direct observations of spatio-temporal charge distributions in Electric double layer capacitors (EDLCs) based on polarizable nanoporous carbonaceous electrode. The negative charge density became the maximum, about 205 $C/m^3$ at the region where was near to collector layer in EDLCs for case $V_{DC}$ = 2.5 V, while the positively charged density became the maximum, about 61.1 $C/m^3$ at the region where it was located around the cathode layer. The PEA measurement used here is a very useful method to quantitively investigates the spatio-temporal charge distribution in EDLCs.

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A Control Design of Energy Storage System for Electric Railway Vehicle Using Supercapacitor (슈퍼커패시터를 이용한 전동차량용 에너지저장시스템의 제어기 설계)

  • Noh, Se-Jin;Lee, Jin-Mok;Son, Kyoung-Min;Choi, Eun-Jin;Choi, Jae-Ho
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.994-995
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    • 2008
  • It is possible to suppress voltage drops, power loading fluctuations and regeneration power lapses for DC railway systems by applying an energy storage system. A electric double layer capacitor (EDLC) of the rapid charge/discharge type has been developed and used in wide ranges. It has a long life, high efficiency and maintenance free/low pollution features as a new energy storage element. In this paper, an efficient charge and discharge control method of a bidirectional DC-DC converter using the supercapacitor is proposed.

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