• 한국결정성장학회지
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• 제18권5호
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• pp.195-199
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• 2008

반도체용 규소 원료는 11 N급의 고순도이나 가격이 고가이고 또한 생산이 제한되어서 폭발적인 태양전지의 수요를 따르지 못하고 있어 저급(5$\sim$6 N)의 UMG(Upgraded Metallurgical Grade)를 사용하자 하는 노력이 진행 중이다. 이 5$\sim$6 N급에서는 dopant 원소인 붕소(B)외 인(P)의 농도가 1 ppm 이상 존재한다. 이들 원료를 사용하여서 결정 성장을 하였을 경우에 존재하는 여러 불순물들의 편석계수(segregation coefficient)를 활용하여 화학적, 전기적 성질을 예상 하여본 결과 결정성장 초기에는 붕소(B)의 농도가 인(P) 보다 높아 p영역이 발생하고 후반부에는 인의 농도가 붕소 보다 높아 n 형 기판이 생성됨을 보았다. 또한 응고속도를 조절하여 여러 불순물을 제거하고자 히는 노력은 편식계수가 적은 금속 일소들의 제거에는 효과적이나 편석계수가 큰 붕소와 인의 제거에는 효과가 크지 않음을 예상 할 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.198-201
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• 2002

In this paper, the dependence of Ni-silicide properties such as sheet resistance and cross-sectional profile on the dopants have been characterized. There was little dependence of sheet resistance on the used dopants such as As, P, $BF_{2}$ and $B_{11}$ just after RTP (Rapid Thermal Process). However, the silicide properties showed strong dependence on the dopants when thermal treatment was applied after formation of Ni-silicide. $BF_{2}$ implanted sample shows the best stable property, while $B_{11}$ implanted one was thermally unstable. The main reason of the excellent property of $BF_{2}$ sample is believed to be the retardation of Ni diffusion by the flourine.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.286-289
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• 1991

We simulated ion implantation and annealing condition of 1 ${\mu}m$ CMOS device using process simulator, SUPREM-II. In this simulation, optimal condition of ion implantation for symmetric threshold voltage determination of PMOS and NMOS region, junction depth and sheet resistance of source/drain region, impurity profile of each region are investigated. Ion implantation dose for 3 ${\mu}m$ N-well junction depth and symmetric threshold voltage of $|0.6|{\pm}0.1$ V were $1.9E12Cm^{-2}$(for phosphorus), $1.7E122Cm^{-2}$(for boron) respectively. Also annealing condition for dopant activation are examined about $900^{\circ}C$, 30 minutes. After final process step, N-well junction, P+ S/D junction and N+ S/D junction depth are calculated 3.16 ${\mu}m$, 0.45 ${\mu}m$ and 0.25 ${\mu}m$ respectively.

• Current Optics and Photonics
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• 제2권1호
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• pp.79-84
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• 2018

We present a novel and simple method to enable spatially selective $ZnAl_2O_4$ nanocrystal formation on the surface of $B_2O_3$-$Al_2O_3$-ZnO-CaO-$K_2O$ glass by employing localized laser heating. Optimized precipitation of glass-ceramics containing nanocrystals doped with $Eu^{3+}$ and $Yb^{3+}$ ions was performed by controlling $CO_2$ laser power and scan speed. Micro-x-ray diffraction and transmission electron microscopy revealed the mean size and morphology of nanocrystals, and energy dispersive x-ray spectroscopy showed the lateral distribution of elements in the imaged area. Laser power and scan speed controled annealing temperature for crystalization in the range of 1.4-1.8 W and 0.01-0.3 mm/s, and changed the size of nanocrystals and distribution of dopant ions. We also report more than 20 times enhanced downshift visible emission under ultraviolet excitation, and 3 times increased upconversion emission from $Eu^{3+}$ ions assisted by efficient sensitizer $Yb^{3+}$ ions in nanocrystals under 980 nm excitation. The confocal microscope revealed the depth profile of $Eu^{3+}$ ions by showing their emission intensity variation.

• 대한전자공학회논문지
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• 제22권2호
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• pp.97-105
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• 1985

PECVD 방법으로 만들어진 도핑한 박막에서 실리콘으로의 인이나 붕소의 확산 특성이 연구되었다. CVD PSC 박막도 역시 만들어면 PECVD PSG에 있는 인의 확산특성과 나란히 비교되었다. 인의 부산은 N2와 O2 분위기 및 1000℃, 1,050℃, 1,100℃의 온도에서 수행되었다. 붕소의 확산 변수들은 B2H2유량 및 박막형성 온도를 달리하여 만들어진 박막에 관하여 고찰되었다. 실리콘으로의 주입물 확산 계수와 확산 Profile이 측정된 혹산 깊이 및 불순물 표면 농도를 써서 Barry의 모델을 적용하여 계산되었다.

• 전자공학회논문지D
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• 제35D권6호
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• pp.37-45
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• 1998

본 논문에서는 본 연구진이 개발 중인 INPROS 3차원 반도체 공정 시뮬레이터 시스템에 이온주입된 불순물의 과도 확산(TED, transient enhanced diffusion) 기능을 첨가하여 수행한 계산 결과를 발표한다. 실리콘 내부에 이온주입된 불순물의 재분포를 시뮬레이션하기 위하여, 먼저 몬테카를로 방법으로 이온주입 공정을 수행하였고, 유한요소법을 이용하여 확산 공정을 수행하였다. 저온 열처리 공정에서의 붕소의 과도 확산을 확인하기 위하여, 에피 성장된 붕소 에피층에 비소와 인을 이온 주입시킨 후, 750℃의 저온에서 2시간 동안 열처리 공정을 수행하였다. 3차원 INPROS 시뮬레이터의 결과와 실험적으로 측정한 SIMS 데이터와 그 결과가 일치함을 확인하였다. INPROS의 점결함 의존성 과도 증속 확산 모델과 소자 시뮬레이터인 PISCES를 이용하여 역 단채널 길이 효과(RSCE, reverse short channel effect)를 시뮬레이션하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.511-515
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• 2013

A Monte Carlo (MC) simulation study has been done in order to investigate the effects of line-edge-roughness (LER) induced by either 1P1E (single-patterning and single-etching) or 2P2E (double-patterning and double-etching) on fully-depleted silicon-on-insulator (FDSOI) tri-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). Three parameters for characterizing the LER profile [i.e., root-mean square deviation (${\sigma}$), correlation length (${\zeta}$), and fractal dimension (D)] are extracted from the image-processed scanning electron microscopy (SEM) image for each photolithography method. It is experimentally verified that two parameters (i.e., ${\sigma}$ and D) are almost the same in each case, but the correlation length in the 2P2E case is longer than that in the 1P1E case. The 2P2E-LER-induced $V_TH$ variation in FDSOI tri-gate MOSFETs is smaller than the 1P1E-LER-induced $V_TH$ variation. The total random variation in $V_TH$, however, is very dependent on the other major random variation sources, such as random dopant fluctuation (RDF) and work-function variation (WFV).

• 전기학회논문지
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• 제60권6호
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• pp.1169-1174
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• 2011

CdTe thin-film solar cell technology is well known that it can theoretically improve its conversion efficiency and manufacturing costs compared to the conventional silicon solar cell technology, due to its optical band gap energy (about 1.45eV) for solar energy absorption, high light absorption capability and low cost requirements for producing solar cells. Although the prior studies obtained the high light absorption, CdTe thin film solar cell has not been come up to the sufficient efficiency yet. So, doping method was selected for the improvement of the electrical characteristics in CdTe solar cells. Some elements including Cu, Ag, Cd and Te were generally used for the p-dopant as substitutional acceptors in CdTe thin film. In this study, the sputtering-deposited CdTe thin film was immersed in $AgNO_3$ solution for ion exchange method to dope Ag ions. The effects of immersion temperature and Ag-concentration were investigated on the optical properties and electrical characteristics of CdTe thin film by using Auger electron spectroscopy depth-profile, UV-visible spectrophotometer, and a Hall effect measurement system. The best optical and electrical characteristics were sucessfully obtained by Ag doping at high temperature and concentration. The larger and more uniform diffusion of Ag ions made increase of the Ag ion density in CdTe thin film to decrease the series resistance as well as mede the faster diffusion of light by the metal ions to enhance the light absorption.

• Current Photovoltaic Research
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• 제3권3호
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• pp.80-84
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• 2015

We suggest new emitter formation method using solid-phase epitaxy (SPE); solid-phase epitaxy emitter (SEE). This method expect simplification and cost reduction of process compared with furnace process (POCl3 or BBr3). The solid-phase epitaxy emitter (SEE) deposited a-Si:H layer by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) on substrate (c-Si), then thin layer growth solid-phase epitaxy (SPE) using rapid thermal process (RTP). This is possible in various emitter profile formation through dopant gas ($PH_3$) control at deposited a-Si:H layer. We fabricated solar cell to apply solid-phase epitaxy emitter (SEE). Its performance have an effect on crystallinity of phase transition layer (a-Si to c-Si). We confirmed crystallinity of this with a-Si:H layer thickness and annealing temperature by using raman spectroscopy, spectroscopic ellipsometry and transmission electron microscope. The crystallinity is excellent as the thickness of a-Si layer is thin (~50 nm) and annealing temperature is high (<$900^{\circ}C$). We fabricated a 16.7% solid-phase epitaxy emitter (SEE) cell. We anticipate its performance improvement applying thin tunnel oxide (<2nm).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.