• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.925-928
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• 2005

In this study, we fabricated the DAMLs using surface micromachining technology as well a low loss coupler for the millimeter-wave band applications using these DAMLs. The structure of DAML is that a signal line is supported on ground plane by dielectric posts. Therefore it has advantages about the loss characteristic and the stable structure. The other advantage of the DAML process is a simple and convenient technique using 4 mask steps, even if it has a micromachining technology. The lowest loss of the fabricated DAML was obtained 2.2 dB/cm at 110 GHz. To obtain the low loss characteristic, couplers were designed and fabricated by using DAMLs. The fabricated ring hybrid coupler has the coupling of 3.58 dB and the thru of 3.31 dB at 60 GHz. We can also obtain the coupling of 3.42 dB, the thru of 3.82 dB from fabricated branch line coupler at 60 GHz.

• Journal of the Korean Vacuum Society
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• v.5 no.3
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• pp.199-205
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• 1996

InGaAs eqitaxial layers have been selectively grown on patterned GaAs(100) substrates by chemical beam epitaxy (CBE) using triethylgallium (TEGa), trimethylindium (TMIn), and unprecracked monoethylarsine (MEAs). Facet growth of InGaAs epilayers has also been investigated at the various growth temperatures and Si4N4 dielectric pattern directions. In [011] jirection of mask, the change from (311), (377) and (111) facets to (311) facet with increasing growth temperature was observed. In [011] direction, however, the change from (011) and (111) facets to (111) facet with increasing growth temperature was observed. These results are attributed to the sidewall growth caused by different surface migration lengths of reactants. The formation of U-shaped (100) top surface is also discussed in terms of dangling bond model.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.63-66
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• 1999

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. Low-dielectric Sr$_2AITaO_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2Cu_3O_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the bottom YBCO edge using plasma treatment prior to deposition of the top YBCO electrode. We investigated the effects of pre-annealing and post-annealing on the characteristics of the interface-treated Josephson junctions. The junction parameters were improved by using in-situ RF plasma cleaning treatment.

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.165-168
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• 2000

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. A low-dielectric Sr$_2$AlTaO$_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2$Cu$_3$O$_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the edge of the YBCO base electrode using high energy ion-beam treatment prior to deposition of the YBCO counter electrode. We investigated the effects of high energy ion-beam treatment, annealing, and counter electrode deposition temperature on the characteristics of the interface-controlled Josephson junctions. The junction parameters such as T$_c$, I$_c$c, R$_n$ were measured and discussed in relation to the barrier layer depending on the process parameters.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.3
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• pp.116-121
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• 2006

Most high-k materials are well known not to be etched easily, Some problems such as low etch rate poor sidewall angle, plasma damage, and process complexity were emerged from the high-density DRAM fabrication. Chemical mechanical polishing (CMP) by a damascene process was proposed to pattern this high-k material was polished with some commercial silica slurry as a function of pH variation. Sufficient removal rate with adequate selectivity to realize the pattern mask of tera-ethyl ortho-silicate (TEOS) film for the vertical sidewall angle were obtained. The changes of X-ray diffraction pattern and dielectric constant by CMP process were negligible. The planarization was also achieved for the subsequent multi-level processes. Our new CMP approach will provide a guideline for effective patterning of high-k material by CMP technique.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.132-132
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• 2010

In the nano-scale Si processing, patterning processes based on multilevel resist structures becoming more critical due to continuously decreasing resist thickness and feature size. In particular, highly selective etching of the first dielectric layer with resist patterns are great importance. In this work, process window for the infinitely high etch selectivity of silicon oxynitride (SiON) layers and silicon nitride (Si3N4) with EUV resist was investigated during etching of SiON/EUV resist and Si3N4/EUV resist in a CH2F2/N2/Ar dual-frequency superimposed capacitive coupled plasma (DFS-CCP) by varying the process parameters, such as the CH2F2 and N2 flow ratio and low-frequency source power (PLF). It was found that the CH2F2/N2 flow ratio was found to play a critical role in determining the process window for ultra high etch selectivity, due to the differences in change of the degree of polymerization on SiON, Si3N4, and EUV resist. Control of N2 flow ratio gave the possibility of obtaining the ultra high etch selectivity by keeping the steady-state hydrofluorocarbon layer thickness thin on the SiON and Si3N4 surface due to effective formation of HCN etch by-products and, in turn, in continuous SiON and Si3N4 etching, while the hydrofluorocarbon layer is deposited on the EUV resist surface.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Applied Science and Convergence Technology
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• v.24 no.3
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• pp.53-59
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• 2015

The field-effect transistors (FETs) with a graphene-based p-n junction channel were fabricated using the patterned self-assembled monolayers (SAMs). The self-assembled 3-aminopropyltriethoxysilane (APTES) monolayer deposited on $SiO_2$/Si substrate was patterned by hydrogen plasma using selective coating poly-methylmethacrylate (PMMA) as mask. The APTES-SAMS on the $SiO_2$ surface were patterned using selective coating of PMMA. The APTES-SAMs of the region uncovered with PMMA was removed by hydrogen plasma. The graphene synthesized by thermal chemical vapor deposition was transferred onto the patterned APTES-SAM/$SiO_2$ substrate. Both p-type and n-type graphene on the patterned SAM/$SiO_2$ substrate were fabricated. The graphene-based p-n junction was studied using Raman spectroscopy and X-ray photoelectron spectroscopy. To implement low voltage operation device, via ionic liquid ($BmimPF_6$) gate dielectric material, graphene-based p-n junction field effect transistors was fabricated, showing two significant separated Dirac points as a signature for formation of a p-n junction in the graphene channel.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.