Fabrication of the interface-treated ramp-edge Josephson junctions using Sr$_2AlTaO_6$ insulating layers

Sr$_2AlTaO_6$ 절연막을 이용한 계면처리된 경사형 모서리 조셉슨 접합의 제작

  • Choi, Chi-Hong (Telecommunications Basic Research Lab., Electronics and Telecommunications Research Institute) ;
  • Sung, Gun-Yong (Telecommunications Basic Research Lab., Electronics and Telecommunications Research Institute) ;
  • Han, Seok-Kil (Telecommunications Basic Research Lab., Electronics and Telecommunications Research Institute) ;
  • Suh, Jeong-Dae (Telecommunications Basic Research Lab., Electronics and Telecommunications Research Institute) ;
  • Kang, Kwang-Yong (Telecommunications Basic Research Lab., Electronics and Telecommunications Research Institute)
  • 최치홍 (한국전자통신연구원, 원천기술연구본부) ;
  • 성건용 (한국전자통신연구원, 원천기술연구본부) ;
  • 한석길 (한국전자통신연구원, 원천기술연구본부) ;
  • 서정대 (한국전자통신연구원, 원천기술연구본부) ;
  • 강광용 (한국전자통신연구원, 원천기술연구본부)
  • Published : 1999.08.18

Abstract

We fabricated ramp-edge Josephson junctions with barriers formed by interface treatments instead of epitaxially grown barrier layers. Low-dielectric Sr$_2AITaO_6$(SAT) layer was used as an ion-milling mask as well as an insulating layer for the ramp-edge junctions. An ion-milled YBa$_2Cu_3O_{7-x}$ (YBCO)-edge surface was not exposed to solvent through all fabrication procedures. The barriers were produced by structural modification at the bottom YBCO edge using plasma treatment prior to deposition of the top YBCO electrode. We investigated the effects of pre-annealing and post-annealing on the characteristics of the interface-treated Josephson junctions. The junction parameters were improved by using in-situ RF plasma cleaning treatment.

Keywords