• Title/Summary/Keyword: depletion width

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An Analytic Model for Punchthrough Limited Breakdown Voltage of Cylindrical Junctions (Punchthrough 원통형 접합이 항복전압에 대한 해석적 모델)

  • 배동건;정상구
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.4
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    • pp.70-76
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    • 1999
  • Analytic model for punchthrough limited breakdown voltage of cylindrical junction is presented as a function of the epitaxial layer thickness and the critical depletion width of the cylindrical junction in nonpunchthrough cases. All the expressions for the distances, electric fields and potentials are normalized, allowing quick determination of the corresponding breakdown voltages. The calculated results are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI.

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An analytic model for planar devices with multiple floating rings (다수의 전계제한링을 갖는 planar소자의 해석적 모델)

  • 배동건;정상구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.6
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    • pp.136-143
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    • 1996
  • A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

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Seoul National University Camera II (SNUCAM-II) : The New SED Camera for Lee Sang Gak Telescope (LSGT)

  • Choi, Changsu;Im, Myungshin
    • The Bulletin of The Korean Astronomical Society
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    • v.42 no.1
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    • pp.35.1-35.1
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    • 2017
  • We present the characteristics and the performance of the new CCD camera system, SNUCAM-II (Seoul National University CAMera system II) that was installed on the Lee Sang Gak Telescope (LSGT) at the Siding Spring Observatory Australia in 2016. SNUCAM-II consists of a deep depletion chip covering a wide wavelength from $0.3{\mu}m$ to $1.1{\mu}m$ with high sensitivity (QE at 90%). It is equipped with SDSS ugriz filters and 13 medium band width (50nm) filters. On LSGT, SNUCAM-II covers $15.7{\times}15.7arcmin$ FOV at pixel scale of 0.92 arcsec and a limiting magnitude of g = 19.91 AB mag at $5{\sigma}$ with 180s exposure time. SNUCAM-II will enable us to study Spectral Energy Distributions (SEDs) of diverse objects from extragalactic sources to solar objects in the southern hemisphere for research and education activities.

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Analytical Model for Breakdown Voltages of InP Diodes (InP 다이오드에서 항복전압의 해석적 모델)

  • Chung, Yong-Sung
    • 전자공학회논문지 IE
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    • v.44 no.1
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    • pp.10-14
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    • 2007
  • Analytical expression for breakdown voltages of InP diodes is induced by employing the effective ionization coefficient extracted from ionization coefficients for electron and hole in InP. The analytical results for breakdown voltage are compared with numerical and experimental results for the doping concentration, $N_D=6\times10^{14}cm^{-3}\sim3\times10^{17}cm^{-3}$. The analytical results show good agreement with the numerical data. Good fits with the experimental results are found for the breakdown voltages within 10% in error at each doping concentration.

The Analysis of I-V characteristics on n-channel offset gated poly-Si TFT`s (Offset 구조를 갖는 n-채널 다결정 실리콘 박막 트랜지스터의 I-V 분석)

  • 변문기;이제혁;김동진;조동희;김영호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.05a
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    • pp.26-29
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    • 1999
  • The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

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Photoreflectance of A $I_x$Ga${1-x}$As(x.<=.0.15) grown by liquid-phase epitaxy (Liquid-phase epitaxy로 성장시킨 A $I_x$Ga${1-x}$As(x.<=.0.15)의 photoreflectance)

  • 배인호;김인수;이철욱;최현태;김말문;김상기
    • Electrical & Electronic Materials
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    • v.7 no.4
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    • pp.300-305
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    • 1994
  • We determined the alloy composition of the liquid-phase epitaxy(LPE) grown $Al_{x}$G $a_{1-x}$ As by the photoreflectance(PR), and observed the variation of PR signal by changing the condition of annealing and thickness of epilayer. As the measuring temperature was decreased, the broadening parameter was decreased, and the amplitude of PR signal was increased. When the temperature of annealing was increased, the surface carrier concentration was decreased and then the shape and amplitude of PR signal were affected by the surface electric field. The structure change was observed when the specimen was annealed for long time at a high temperature. We found that the surface electric field increased when the thickness of epilayer was decreased by etching, because the band bending was increased by the decreased of the width of depletion layer....

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Analytic Threshold Voltage Model of Recessed Channel MOSFETs

  • Kwon, Yong-Min;Kang, Yeon-Sung;Lee, Sang-Hoon;Park, Byung-Gook;Shin, Hyung-Cheol
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.61-65
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    • 2010
  • Threshold voltage is one of the most important factors in a device modeling. In this paper, analytical method to calculate threshold voltage for recessed channel (RC) MOSFETs is studied. If we know the fundamental parameter of device, such as radius, oxide thickness and doping concentration, threshold voltage can be obtained easily by using this model. The model predicts the threshold voltage which is the result of 2D numerical device simulation.

Capacitance Characteristics of GaAs MESFET will Temperatures (온도 변화에 따른 GaAs MESFET의 정전용량에 대한 연구)

  • 박지홍;김영태;원창섭;안형근;한득영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.11a
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    • pp.445-448
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    • 1999
  • In this Paper, we present simple physical model of the Capacitance characteristics for GaAs MESFET\`s in wide temperatures. In this model, gate-source and gate-drain capacitances are represented by analytical expressions which are classified into three different regions for bias voltage. This model contained the temperature dependent variable that is the built-in voltage and the depletion width. Using the equations obtained in this work a submicron gate length MESFET has simulated and theoretical result are in good agreement with the experimental measurement.

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C-V Characteristics of GaAs MESFETs (GaAs MESFET의 정전용량에 관한 특성 연구)

  • 박지홍;원창섭;안형근;한득영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.11
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    • pp.895-900
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    • 2000
  • In this paper, C-V characteristics based on the structure of GaAs MESFET’s has been proposed with wide range of applied voltages and temperatures. Small signal capacitance; gate-source and gate-drain capacitances are represented by analytical expressions which are classified into two different regions; linear and saturation regions with bias voltages. The expression contains two variables; the built-in voltage( $V_{vi}$ )and the depletion width(W). Submicron gate length MESFETs has been selected to prove the validity of the theoretical perdiction and shows good agreement with the experimental data over the wide range of applied voltages.

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The Schottky Diode of Optimal Stepped Oxide Layer for High Breakdown Voltage (높은 항복전압을 위한 최적 계단산화막의 쇼트키 다이오드)

  • Lee, Yong Jae;Lee, Moon Key;Kim, Bong Ryul
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.4
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    • pp.484-489
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    • 1986
  • A device with variable stepped oxide layer along the edge region of Schottky junction have been designed and fabricated. The effect of this stepped oxide layer in the edge region improves the breakdown voltage as a result of the by increase of the depletion layer width, and decreases the leakage current as compared to the effect of conventional field oxide layer, when the reverse voltage was applied. Experimental results shown that the Schottky diode with the the reverse voltage was applied. Experimenal results show that the Schottky diode with the optimal stepped oxide layer maintains nearly ideal I-V characteristics and excellent breakdown voltage(170V) by reducing the edge effect inherent in metal-semiconductor contacts. The optimal conditions of stepped oxide layer are 1700\ulcornerin thickness and 10\ulcorner in length.

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