• Journal of the Korean Society of Industry Convergence
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• v.2 no.2
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• pp.103-108
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• 1999

The paper describes a implementation of space vector pulse-width modulation voltage source inverter and interfacing of DSP using field programmable gate array(FPGA) for a induction motor vector control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QLl6X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed Application Specific Integrated Circuit(ASIC) for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance induction motor drives with a voltage source inverter. Simulation and implementation results are shown to verify the usefulness of ASIC in a motor drive system and power electronics applications.

• Journal of Advanced Marine Engineering and Technology
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• v.3 no.1
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• pp.19-31
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• 1979

Recently the adaptive control system, which keeps the control system always optimal by adjusting the control parameters automatically according to the variations of the plant parameters, have become very important in the field of control engineering. The adaptive control systems are usally composed of the plant identification, the decision of the optimal control parameters, and the adjustment of the control parameters. This paper deals with a method of the adaptive control system when PI or PID controller is used in the feed back control system. Its controlled object (the plant) is assumed to be described by the transfer function of $\frac{ke^{-LS}}{1+TS}$ where k, T and L are steady state gain, time constant and pure dead time respectively, and their values are variable in accordance with the change of environmental circumstance. It has been known that a pseudo-random binary signal is quite effective for the measurement of an impulse response of a plant. In adaptive control systems, however, the impulse response itself is not appropriate to determine the control parameters. In this paper, the authors propose a method to estimate directly the parameters of the plant k, T and L by means of the correlation technique using 3 level M-sequence signal as a test signal. The authors also propose a method to determine the optimal parameters of the PI or PID controller in the sense of minimizing the square integral of the control error in the feed back control system, and the values of the optimal parameters are computed numerically for various values of T and L, and the results are examined and compared with those of the conventional methods. Finally the above-mentioned two methods are combined and an algorithm to struct an adaptive control system is suggested. The experiments for the indicial responses by means of both the model of the temperature control system using SCR actuater and the analog simulations have shown good results as expected, and the effectiveness of the proposed method is verified. The M-sequence generator and the time delay circuit, which are manufactured for the experiments, are operated in quite a good condition.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.1
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• pp.58-64
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• 2016

This study presents a design method for a single-loop voltage controller that is suitable for an arbitrary waveform generator (AWG). The voltage control algorithm of AWG should ensure high dynamic performance and should attain sufficient robustness to disturbances such as inverter nonlinearity, sensor noise, and load current. By analyzing the power circuit of AWG, control limitation and control target are presented to improve the dynamic performance of AWG. The proposed voltage control algorithm is composed of a single-loop output voltage control, an inverter current feedback term to improve transient response, and a load current feedforward term to prevent voltage distortion. The guideline for setting control gain is presented based on output filter parameters and digital time delay. The performance of the proposed algorithm is proven by experimental results through comparison with the conventional algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.5
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• pp.409-415
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• 2012

This paper presents a new software-based on-line dead-time compensation technique for a single-phase grid-connected photovoltaic (PV) inverter system. To prevent a short circuit in the inverter arms, a switching delay time must be inserted in the pulse width modulation (PWM) signals. This causes the dead-time effect, which degrades the system performance around zero-crossing point of the output current. To reduce the dead-time effect around the zero-crossing point of grid current, a harmonic mitigation of grid current is used as an additional part of the synchronous frame current control scheme. This additional task mitigates the harmonic components caused by the dead-time from the grid current. Simulation and experimental results are shown to verify the effectiveness of the proposed dead-time compensation method in the single-phase grid-connected inverter system.

• The Magazine of the IEIE
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• v.23 no.11
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• pp.89-100
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• 1996

A new stage-sliced pipiline structure is presented to design a high speed real time Global Positional Systems(GPS) applications. The CORDIC algorothm was revised to generate a pipeline structure, which will be used to produce a large amount of trigonometric computations rapidly. A stage-sliced approach was introduced to adjust the number of interative processes, and thereby to control the precision of computation results. Both the computation and the control circuits of the proposed architecture are included in a pipeline stage, which are intergrated into a stage slice. The circuit was prototyped using six FPGA chips : one is used for glue logics and five of the chips are used for pipeline slice implementation. A single FPGA chip comprising 7 pipeline stages provides one pipeline slice. To compensate and inter-slice time delay, dummy cycles are introduced in inter-slice signal exchanges.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.479-484
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• 2016

In this paper, a design of DC level shifter transmitting and receiving control and data signal which have various DC level through daisy chain interface between master IC and slave is introduced in the cell voltage monitoring (CVM). Circuit designed with a latch structure have a function to operate in high speed and for output of variable DC level through transmission gate. As a result of the simulation and the measurement, it was confirmed that control and data signal could be transferred according to the change of DC level from 0V to 30V. Delay time was measured about 170ns. but, it was considered as a negligible tolerance due to a parasitic capacitance of measuring probe and test board.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.50-56
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• 2015

An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.23-30
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• 2012

This paper proposes a novel adaptive header-based power gating structure to compensate for the performance loss and the increased wake-up time of the power gating structures induced by the negative bias temperature instability (NBTI) effect. The proposed structure consists of variable width footers based on the two-pass power gating and a new NBTI sensing circuit for an adaptive control. The simulation results of the proposed structure are compared to those of power gating without the adaptive control and show that both the circuit-delay and wake-up time dependence of the power gating structure on the NBTI stress is minimized with only 3% and 4% increase, respectively while keeping small leakage power and rush-current. In this paper, a 45 nm CMOS technology and predictive NBTI model have been used to implement the proposed circuits.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.4
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• pp.155-160
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• 2003

In this study, an Alexandrite laser system for hair removal adopting a multi-discharge method in which three flash lamps are turned on consecutively was designed and fabricated to examine the pulse width and the pulse shape of the laser beams depending upon the changes in the lamp turn-on time. Specifically, this study demonstrates a technology that makes it possible to formulate various pulse shapes by turning on three flashlamps consecutively on a real-time basis with the aid of a PIC (program integrated circuit) one-chip microprocessor. With this technique, the lamp turn-on delay time can be varied more diversely from 0 to 10 ms and real-time control is possible with an external keyboard, enabling an assortment of pulse shapes. In addition, longer pulses can be more widely used for industrial processing as well as for numerous medical purposes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.94-97
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• 2007

The desin and implementation of a CMOS analog integrated circuit that provides dual-mode modulations, PWM for active clamp reset converter and PFM for LLC resonant converter, is described. The proposed controller is capable of implementing programmable soft start and current-mode control with compensating ramp for PWM and frequency shifting soft start for PFM. Also it provides delay time for both modes. PWM mode is implemented by active clamp reset converter and PFM mode is implemented by LLC resonant convereter, respectively. The chip is fabricated using the 0.6um high voltage CMOS process.