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Design of DC Level Shifter for Daisy Chain Interface

Daisy Chain Interface를 위한 DC Level Shifter 설계

  • 여성대 (서울과학기술대학교 NID융합기술대학원) ;
  • 조태일 (서울과학기술대학교 NID융합기술대학원) ;
  • 조승일 (일본 Yamagata Univ. Innovation Center for Organic Electronics) ;
  • 김성권 (서울과학기술대학교 NID융합기술대학원)
  • Received : 2016.05.20
  • Accepted : 2016.05.24
  • Published : 2016.05.31

Abstract

In this paper, a design of DC level shifter transmitting and receiving control and data signal which have various DC level through daisy chain interface between master IC and slave is introduced in the cell voltage monitoring (CVM). Circuit designed with a latch structure have a function to operate in high speed and for output of variable DC level through transmission gate. As a result of the simulation and the measurement, it was confirmed that control and data signal could be transferred according to the change of DC level from 0V to 30V. Delay time was measured about 170ns. but, it was considered as a negligible tolerance due to a parasitic capacitance of measuring probe and test board.

본 논문은 Daisy Chain 구조의 CVM(:Cell Voltage Monitoring) 시스템에서, 다양한 DC Level을 갖는 Master IC와 Slave IC 사이에 명령 Data 신호의 전달을 가능하게 해주는 DC Level Shifter 설계를 소개한다. 설계한 회로는 래치 구조가 적용되어 고속 동작이 가능하고, 출력단의 Transmission Gate를 통하여 다양한 DC Level이 출력되도록 설계하였다. 시뮬레이션 및 측정 결과, 0V에서 30V까지의 DC Level 변화에 따른 제어 및 Data 신호의 전달을 확인하였다. Delay Time 오차는 약 170ns가 측정되었지만, 측정 Probe의 Capacitance 성분 및 측정 Board의 영향을 고려하면, 무시할 수 있을 정도의 오차로 간주된다.

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