• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.9
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• pp.1837-1844
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• 2009

In this paper, the circuit of 2 variable ternary adder and multiplier circuit using current mode CMOS are implemented. The presented ternary adder circuit and multiplier circuit using current mode CMOS are driven the voltage levels. We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under $0.18{\mu}m$ CMOS standard technology, $5{\mu}A$ unit current in $0.54{\mu}m/0.18{\mu}m$ ratio of NMOS length and width, and $0.54{\mu}m/0.18{\mu}m$ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit show the propagation delay time $1.2{\mu}s$, operating speed 300KHz, and consumer power 1.08mW.

• Journal of Power Electronics
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• v.18 no.2
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• pp.640-650
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• 2018

A TRIAC dimmable LED driver with a wide tuning range and a two-stage uniform dimming scheme is proposed in this paper. To solve the restricted dimming range problem caused by the limited conduction ratio of TRIAC dimmers, a conduction ratio compensation technique is introduced, which can increase the output current up to the rated output current when the TRIAC dimmer turns to the maximum conduction ratio. For further optimization, a two-stage uniform dimming diagram with a rapid dimming curve and a slow dimming curve is designed to make the LED driver regulated visually uniform in the whole adjustable range of the TRIAC dimmer. The proposed control chip is fabricated in a TSMC $0.35{\mu}m$ 5V/650V CMOS/LDMOS process, and verified on a 21V/500mA circuit prototype. The test results show that, in the 90V/60Hz~132V/60Hz ac input range, the voltage linear regulation is 2.6%, the power factor is 99.5% and the efficiency is 83%. Moreover, in the dimming mode, the dimming rate is less than 1% when the maximum dimming current is 516mA and the minimum dimming current is only about 5mA.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.755-758
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• 2002

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary N- and P-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors far the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 ${\mu}$m n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing ${\pm}$2.4 V under ${\pm}$2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits. The applications of the proposed CCII to current-mode filters are also described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• ETRI Journal
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• v.37 no.6
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• pp.1154-1164
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• 2015

This paper proposes a fully sensorless driver for a permanent magnet synchronous motor (PMSM) integrated with a digital motor controller and an analog pre-driver, including sensing circuits and estimators. In the motor controller, a position estimator estimates the back electromotive force and rotor position using a sliding-mode observer. In the pre-driver, drivers for the power devices are designed with a level shifter and isolation technique. In addition, a current sensing circuit measures a three-phase current. All of these circuits are integrated in a single chip such that the driver achieves control of the speed with high accuracy. Using an IC fabricated using a $0.18{\mu}m$ BCDMOS process, the performance was verified experimentally. The driver showed stable operation in spite of the variation in speed and load, a similar efficiency near 1% compared to a commercial driver, a low speed error of about 0.1%, and therefore good performance for the PMSM drive.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.921-926
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• 2003

This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

• Proceedings of the KIEE Conference
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• summer
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• pp.1214-1216
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• 2004

Conventional Switched Mode Power Supplies(SMPS) with diode-capacitor rectifier have distorted input current waveform with high harmonic contents. Typically, these SMPS have a power factor lower than 0,65. To improve with this problem the power factor correction(PFC) circuit of power supplies has to be introduced. PFC circuit have tendency to be applied in new power supply designs. The input active power factor correction circuits can be implemented using either the two-stage or the single-stage approach. In this paper, the comparative analysis of power factor correction circuit using feedforward control with average current mode single-stage flyback method converter and two-stage converter which is combination of boost and flyback converter. The two prototypes of 50W were designed and tested a laboratory experimental. Also, the comparative analysis is confirmed by simulation and experimental results.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.85-93
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• 2007

This paper presents new LVDS I/O circuits with a high noise margin for use in highly parallel I/O environments. The proposed LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and a output stage with common mode feedback(CMFB). The differential phase splitter generates a pair of differential signals which have a balanced duty cycle and $180^{\circ}$ phase difference over a wide supply voltage variation due to SSO(simultaneous switching output) noises. The CMFB output stage produces the required constant output current and maintains the required VCM(common mode voltage) within ${\pm}$0.1V tolerance without external circuits in a SSO environment. The proposed receiver circuits in this paper utilizes a three-stage structure(single-ended differential amp., common source amp., output stage) to accurately receive high-speed signals. The receiver part employs a very wide common mode input range differential amplifier(VCDA). As a result, the receiver improves the immunities for the common mode noise and for the supply voltage difference, represented by Vgdp, between the transmitter and receiver sides. Also, the receiver produces a rail-to-rail, full swing output voltage with a balanced duty cycle(50% ${\pm}$ 3%) without external circuits in a SSO environment, which enables correct data recovery. The proposed LVDS I/O circuits have been designed and simulated with 0.18um TSMC library using H-SPICE.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.