• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.10a
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• pp.185-190
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• 1995

Conventional alarm system has many difficulties in the operator's identifying the plant status during special situations such as design basis accidents. To solve the shortcomings, an on-line alarm annunciator system, called dynamic alarm console (DAC), was developed. In the DAC, a signal is generated as alarm by the use of an adaptive setpoint check strategy based on operating mode, and time delay technique is used not to generate nuisance alarms. After alarm generation, if activated alarm is a level precursor alarm or a consequencial alarm, it would be suppressed, and the residual alarms go through dynamic prioritization which provide the alarms with pertinent priorities to the current operating mode. Dynamic prioritization is achieved by going through the system- and mode-oriented prioritization. The DAC has the alarm hierarchical structure based on the physical and functional importance of alarms. Therefore the operator can perceive alarm impacts on the safety or performance of the plant with the alarm propagation from equipment level to plant functional level. In order to provide the operator with the most possible cause of the event and quick cognition of the plant status even without recognizing the individual alarms, reactor trip status tree (RTST) was developed. The DAC and the RTST have been simulated with on-line data obtained from the full-scope simulator for several abnormal cases. The results indicated that the system can provide the operator with useful and compact information fur the earlier termination and mitigation of an abnormal state.

• Applied Chemistry for Engineering
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• v.35 no.2
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• pp.85-95
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• 2024

Direct air capture (DAC) technology plays a crucial role in mitigating climate change. Reports from the International Energy Agency and climate change emphasize its significance, aiming to limit global warming to 1.5 ℃ despite continuous carbon emissions. Despite initial costs, DAC technology demonstrates potential for cost reductions through research and development, operational learning, and economies of scale. Recent advancements in high-permeance polymer membranes indicate the potential of membrane-based DAC technology. However, effective separation of CO₂ from ambient air requires membranes with high selectivity and permeability to CO₂. Current research is focusing on membrane optimization to enhance CO₂ capture efficiency. This study underscores the importance of direct air capture, evolving cost trends, and the pivotal role of membrane development in climate change mitigation efforts. Additionally, this research delved into the theoretical background, conditions, composition, advantages, and disadvantages of permeance and selectivity in membrane-based DAC.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.549-552
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• 2004

The thesis describes the design of 12bit digital-to-analog converter (DAC) which shows the conversion rate of 500MHz and the power supply of 3.3V with 0.35${\mu}m$ CMOS 1-poly 4-metal process for advanced wireless transceiver of high speed and high resolution. The proposed DAC employes segmented structure which consists of 6bit MSB, 3bit mSB, 3bit LSB for area efficiency Also, using a optimized aspect ratio of process and new triple diagonal symmetric centroid sequence for high yield and high linearity. The proposed 12bit current mode DAC was employs new deglitch circuit for the decrement of the glitch energy. Simulation results show the conversion rate of 500MHz, and the power dissipation of 85mW at single 3.3V supply voltage. Both DNL and INL are found to be smaller than ${\pm}0.65LSB/{\pm}0.8LSB$.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.6
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• pp.1600-1619
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• 2023

Organizations and other institutions have recently started using cloud service providers to store and share information in light of the Internet of Things (IoT). The major issues with this storage are preventing unauthorized access and data theft from outside parties. The Block chain based Security Sharing scheme with Data Access Control (BSSDAC) was implemented to improve access control and secure data transaction operations. The goal of this research is to strengthen Data Access Control (DAC) and security in IoT applications. To improve the security of personal data, cypher text-Policy Attribute-Based Encryption (CP-ABE) can be developed. The Aquila Optimization Algorithm (AOA) generates keys in the CP-ABE. DAC based on a block chain can be created to maintain the owner's security. The block chain based CP-ABE was developed to maintain secures data storage to sharing. With block chain technology, the data owner is enhancing data security and access management. Finally, a block chain-based solution can be used to secure data and restrict who has access to it. Performance of the suggested method is evaluated after it has been implemented in MATLAB. To compare the proposed method with current practices, Rivest-Shamir-Adleman (RSA) and Elliptic Curve Cryptography (ECC) are both used.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.378-386
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• 2017

A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.269-274
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• 2004

Current delivery system, in which the analog current produced by a unique DAC circuit is stored into a current-memory circuit and delivered in a time-divided sequence, shows variation of output current as low as 4% in a current source data-driver IC for AM-OLED driven by a current-programmed method without any fuse repairing after fabrication. This driver IC has 54 outputs and can sink constant current as low as 3 ${\mu}A$ with 6-bit analog levels. Such a low current level without variation can hardly be obtained by an ordinary MOS transistor because the current level is in the sub-threshold region and changes exponentially with threshold voltage variation. Thus we adopted a current mirror circuit composed of bipolar transistors to supply well-controlled current within a nano-ampere range.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.231-234
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• 2002

A transceiver for ADSL systems contains an interpolated combfilter, halfband filters, oversampling sigma delta modulator, a current steering DAC and an analog filler. The circuit complexity of the architecture makes it necessary to use behavioral models to determine the system features. For this reason, we need a specific behavioral simulation environment using the Matlab program. The Matlab is crucial for these circuits to be rapidly incorporated in larger systems, in particular in the context of mixed-signal-test schemes. Design trade-off among the blocks has also been discussed. The design methodology is based on behavioral design and CMOS process.