• The Journal of Korean Institute of Communications and Information Sciences
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• v.7 no.2
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• pp.47-54
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• 1982

In this paper, a improved per-channel PCM Coder with 1-bit interpolation is proposed. The coder converts a telephone signal to 15-segments u-law PCM signal of a large dynamic range. The A/D conversion technique of the proposed converter requires a feedback loop around a quantizer operates at high speed, and a accumulater for accumulating the quantized values to provide PCM outputs. To obtain both linear and compressed PCM signals a improved table look-up method is presented. The operations of the proposed converter are certified through the experiments to be good. The experimental circuit comprises TTL logic gates, a resistive D/Z converter and a simple differential amplifier. From the results of the experiments, it is known that the proposed converter has many advantage to be adopted economically for per-channel onverter used in rural area service.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.1
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• pp.53-62
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• 2023

Due to the recent increase in new and renewable energy, gas turbine generators start and stop every day to supply high-quality power, and accordingly, the life span of high-temperature parts is shortened and the failure of combustion chamber temperature sensors increases. Therefore, in this study, we proposed a fuzzy logic-based failure diagnosis algorithm that can accurately diagnose and systematically detect the failure of the sensor when the dual temperature sensor used for gas turbine control fails, and to confirm the usefulness of the proposed algorithm We tried to confirm the usefulness of the proposed algorithm by performing various simulations under the matlab/simulink environment.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.12B
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• pp.1548-1555
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• 2011

In ultra-deep submicron technology, minimization of propagation delay and power consumption on buses is one of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. Most of the previous works on bus encoding are targeted either to minimize the bus switching or minimize the crosstalk delay, but not both. This paper proposes a new bus encoding scheme which can adaptively select one of functions "invert" and "logic-convert" according the number of bus switching on an encoded 4-bit cluster. This scheme leads to minimization of both crosstalk and bus switching. In experiment result, our proposed encoding technique consumes about 25% less power over the previous, while completely eliminating the crosstalk delay.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1587-1599
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• 2017

This paper proposes a real-time implementation of an optimal operation of a double stage grid connected wind power system incorporating an active power filter (APF). The system is used to supply the nonlinear loads with harmonics and reactive power compensation. On the generator side, a new adaptive neuro fuzzy inference system (ANFIS) based maximum power point tracking (MPPT) control is proposed to track the maximum wind power point regardless of wind speed fluctuations. Whereas on the grid side, a modified predictive current control (PCC) algorithm is used to control the APF, and allow to ensure both compensating harmonic currents and injecting the generated power into the grid. Also a type 2 fuzzy logic controller is used to control the DC-link capacitor in order to improve the dynamic response of the APF, and to ensure a well-smoothed DC-Link capacitor voltage. The gained benefits from these proposed control algorithms are the main contribution in this work. The proposed control scheme is implemented on a small-scale wind energy conversion system (WECS) controlled by a dSPACE 1104 card. Experimental results show that the proposed T2FLC maintains the DC-Link capacitor voltage within the limit for injecting the power into the grid. In addition, the PCC of the APF guarantees a flexible settlement of real power exchanges from the WECS to the grid with a high power factor operation.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2307-2309
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• 2004

This paper presents a modeling and simulation of a fuzzy controller for maximum power extraction of a grid-connected wind energy conversion system with a link of a rectifier and an inverter. It discusses the maximum power control algorithm for a wind turbine and proposes, in a graphical form, the relationships of wind turbine output, rotor speed, power coefficient, tip-speed ratio with wind speed when the wind turbine is operated under the maximum power control. The control objective is to always extract maximum power from wind and transfer the power to the utility by controlling both the pitch angle of the wind turbine blades and the inverter firing angle. Pitch control method is mechanically complicated, but the control performance is better than that of the stall regulation method. The simulation results performed on MATLAB will show the variation of generator's rotor angle and rotor speed, pitch angle, and generator output.

• Transactions of the Korean Society of Automotive Engineers
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• v.4 no.3
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• pp.102-111
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• 1996

For the air-fuel ratio control in a fuel injection SI engine, the Jump-Ramp control algorithm has been widely adopted by using the on/off type oxygen sensor. But the Jump-Ramp control method has limitation on treating the frequency and amplitude of the air-fuel ratio oscillation. This study suggests another feedback control logic named modulated fuel feedback control, which has a concept of pre-tuned air-fuel ratio oscillation. In the modulation method, the oxygen sensor output is not treated as on/off signal but as analog signal for feedback. By using the modulation method, the frequency and the amplitude of air-fuel ratio oscillation can be adjustable to some extent for improving the conversion efficiency of the Three-Way Catalyst. The result shows that the performance of the modulation method is better than that Jump-Ramp control method in reducing the amplitude of the air-fuel ratio oscillation as well as in increasing the frequency of the air-fuel ratio oscillation.

• Journal of the Korea Society of Computer and Information
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• v.14 no.3
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• pp.13-26
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• 2009

In this raper, We propose the alternative solution, RTOS-based system to replace the PLC 4hat has used the automation system for industrial processes. RTOS-based system is constructed the PC and RTOS as hardware and software. It overcomes the limit of PLC and guarantees the stability and reliability. Also, PC has better performance and cheaper than PLC when operating and constructing the system. For many manufactures, these benefits alone are all the reason they need to switch from PLC-based system to RTOS-based system. To use the RTOS-based System, the PLC program needs the conversion to the RTOS task. And how to transform is the most important issue. So, we propose conversion method through the system model. The system model defines the operation of each module as the task after the system divided into module. Because the system divided into modules can control, the performance and the functionality of system improve, and the system can deal with a problem easily when repairing and changing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.