• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.55-58
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.276-280
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• 2003

This paper presents a zero voltage and zero current switching (ZVZCS) interleaving two-transistor forward converter for high input voltage and high power application. A phase shift has a disadvantage that a circulating current and RMS current stress, conduction losses of transformer and switching devices increases. Due to this circulating current and RMS current stress, conduction losses of transformer and switching devices increases. To alleviate these problems, we propose an improved interleaving two-transistor forward Zero Voltage and Zero Current Switching (ZVZCS) dc/dc converter using a tapped inductor a snubber capacitor and two snubber diodes attached at the secondary side of transformer. The proposed ZVZCS converter is verified on a 1.8kW, 5kHz experimental prototype.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.644-647
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• 2007

We have fabricated vertical type organic thin film transistor using tris-8-hydroxyquinoline aluminum $(Alq_3)$. The effects of the growth control of $Alq_3$ thin layer on the grain structure and the flatness of film surface have been investigated. In addition, we have fabricated light emitting transistor and then investigated electroluminescent properties.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.227-233
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• 2010

This paper treats the method to build up Motor drive-circuit using semi-conduct control part like power transistor, MOSEFT and refers to the operation theory, forward, reverse rotation control and speed control method which is changed by PWM. And also, this paper mention to the basic principle of DC Motor and various Motor control method using micro-processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.5
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• pp.1-6
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• 1973

The paper deals with a study on an electronic watering device. The system is designed to scan 10 probes so that they detect moisture of soil. Input potentials are compared with reference level before the system is watering. rt provides a main clock oscillator and a control oscillator for the system control, and a programmable unijunction transistor is used for the control circuit. The reference levels are adjustable so as to water various soils. The device is tested for two different sails of moisture content ranging from 6 to 51%. It works at any input level higher than 0.6 V compared to the reference level.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.546-549
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a Matlab program.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.381-382
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• 2018

Subthreshold swings (SSs) and on-currents of four types of junctionless nanowire tunnel field-effect transistor(JLNW-TFET) are observed. Ge-Si structure for the source-channel junction has the highest drive current among Si-Si, Si-Ge, and Ge-Ge junction, and the drive current increases up to 1000 times compared to others. Minimum SS of Si-Si junction is reduced by up to 5 times more than others.

• Journal of Power Electronics
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• v.15 no.1
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• pp.131-145
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• 2015

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.