• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.137-140
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• 2000

This paper proposes an improved soft switching two-transistor forward converter which uses a novel lossless snubber circuit to effectively control the turn-off dv/dt rate of the main transistors. In the proposed soft switching implementation the turn-off voltage traces across the main two transistors are almost the same contributing to reduce the total capacitive turn-on loss and the snubber current is divided into the two transistors resulting in distributed thermal stresses

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.170-171
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• 2016

A surface potential model is introduced for L-shaped tunnel field-effect-transistor(L-TFET). Excellent agreement is obtained when model results are compared with TCAD data.

• Bulletin of the Korean Chemical Society
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• v.35 no.3
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• pp.731-736
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• 2014

An organic junction transistor with a vertical structure based on an active layer of poly(3-hexylthiophene) was fabricated by facile micro-contact printing combined with the Langmuir-Schaefer technique, without conventional e-beam or photo-lithography. Direct printing and subsequent annealing of Au-nanoparticles provided control over the thickness of the Au electrode and hence control of the electrical contact between the Au electrode and the active layer, ohmic or Schottky. The junction showed similar current-voltage characteristics to an NPN-type transistor. Current through the emitter was simply controllable by the base voltage and a high transconductance of ~0.2 mS was obtained. This novel fabrication method can be applied to amplifying or fast switching organic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.167-168
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• 2007

Design Rule이 작아짐에 따라 Transistor performance 향상을 위한 여러 방안중 SEG 공정이 적용되고 있으며 이에 따른 Transistor 특성 연구 결과이다. SEG공정 적용시 SEG Profile에 따라 Transistor의 Short Channel Effect 열화가 발생하였고 그 원인은 Sidewall Facet발생으로 추정되며 이를 개선시 Tr 특성이 개선됨을 확인하였다.

• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.166-170
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• 2003

This paper presents the TTFC(Two Transistor Forward Converter) using Synchronous Rectifier of Compulsory Control-driver. The two transistor forward circuit is used to decrease voltage stress of primary side and the synchronous rectifier is used to reduce current stress of secondary side. Previous synchronous rectifier's MOSFET of TTFC have long dead time This paper presents synchronous rectifier of compulsory control-driver for minimized dead time. This paper compared with diode rectifier, self-driven synchronous rectifier and compulsory control-driver synchronous rectifier of TTFC. The principle of operation, feature and design considerations are illustrated and verified through the experiment with a 200W 100kHz MOSFET based experimental circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.931-937
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• 2003

The principle of the superconducting vortex flow transistor (SVFT) is based on control of the Abrikosov vortex flowing along a channel. The induced voltage is controlled by a bias current and a control current, instead of external magnetic field. The device is composed of parallel weak links with a nearby current control line. We explained the process to get an I-V characteristic equation and described the method to induce the external and internal magnetic field by the Biot-Savarts law in this paper. The equation can be used to predict the I-V curves for fabricated device. From the equation we demonstrated that the current-voltage characteristics were changed with input parameters. I-V characteristics were simulated to analyze a SVFT with multi-channel by a computer program.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.173-174
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• 2013

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.