• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.117-125
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• 2004

Performing the sensitivity analysis of contact conduction on the basis of the thermal model already established, the study of thermal design is accomplished for the preparation of the future changes of mechanical interface design. A relatively simple thermal model is taken into consideration for the convenience of the analysis. A variety of the spacecraft bus voltages and the contact resistances are tried. As a consequence, when the mechanical interface condition is changed at the same module, the successful thermal design could be achieved if we design the heater to have sufficiently large power with reference to the heritage of contact resistance.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.73-77
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• 2002

Characteristics of Cu/Si/Cu ohmic contacts to n-type 4H-SiC were investigated systematically. The ohmic contacts were formed by rf sputtering of multi layer Cu/Si/Cu sputtered sequentially. The annealings were peformed With 2-Step using RTP in vacuum ambient. The specific contact resistivity($\rho$c), sheet resistance(Rs), contact resistance(Rc), transfer length(L$_{T}$) were calculated from resistance(R$_{T}$) versus contact spacing(d) measurements obtained from TLM(transmission line method) structure. Best results were obtained for a sample annealed at vacuum as $\rho$c = 1.0x10$^{-6}$ $\Omega$$\textrm{cm}^2$, Rc = 2$\Omega$ and L$_{T}$ = 1${\mu}{\textrm}{m}$. The physical properties of contacts were examined using XRO and AES. The results showed that copper silicide was formed on SiC and Cu was migrated into SiC.o SiC.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.65-65
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• 2010

본 논문은 이 중 직렬저항에서 한 부분을 차지하고 있는 전극부분과 리본부분의 접촉저항이 단순히 접촉 면적만이 아닌 위치에 따라서 다른 값을 지닌다는 전제에 연구를 하였다. 값이 작은 접촉저항의 명확히 눈에 보이는 결과를 위해서 접촉저항이 무한대가 되었을 때, 즉 전극과 리본이 박리가 된 상태를 기준으로 실험을 하였고, 그 이유를 증명하기위해 태양전지를 세부분으로 나누어 전류발생량을 측정하였고, 전극을 세부분으로 나눈 뒤 I-V curve를 측정하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.969-974
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• 1987

High value sheet resistance (Rs, 350 \ulcorner/ -80 K \ulcorner/ ) borom implanted polysilicon resistors were fabricated under process condition compatible with bipolar integrated circuits fabrication. This paper includes the effect of contact ion implantation on Rs and the effect of electron gun(e-gun) deosition vs. non e-gun evaporated metal contacts on the Rs. From results, we observed that the contact ion implanted samples showed higher Rs value than those without contact ion implantation. Also, it was shown that there is noticeable amount of Rs degradation for e-gun samples, while sputtered samples expressed little Rs degradation after PtSi was formed.

• Journal of the Korean Geophysical Society
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• v.2 no.3
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• pp.225-233
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• 1999

Electrical resistivity of a rock-sample is dependant on not only formation factor of rock itself but also many parameters such as fluid type, measuring device, temperature, water saturation, electrical contact between electrode and core section, induced polarization, and frequency of electric source. In this study, we attempt to verify various affecting factors in core resistivity measurements and to find a better environment for core resistivity measurement. Particularly great attention has been paid to understanding the effects of temperature, water saturation, contact condition between sample and electrodes, and frequency of electric source. Precise measurement of resistivity can be achieved by utilizing silver paste for better contacts, taping samples for constant moisture contents, and using time-series resistivity data.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.179-180
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• 2007

반도체의 최소 회로 선폭이 감소함에 따라 Contact 저항이 크게 증가하게 된다. Contact 저항을 낮추기 위하여 Tungsten Metal Contact을 일반적으로 사용하며, Si 기판과의 Ohmic 접촉 및 WF6의 Fluorine과 Si 반응을 억제하기 위한 Barrier Metal로 Ti/TiN 이중막을 사용한다. 본 논문에서는 90nm급 이하 제품의 CVD Ti/TiN Barrier Metal이 유발하는 불량 현상과 원인 규명에 대하여 연구하였으며, Ohmic Contact형성을 위해 TiSix형성 최적화 방안에 대해 정리하였다.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.17-23
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• 2013

As a basic research to develop stretchable electronic packaging technology, CNT-Ag composite pads were formed on top of Cu/Sn chip bumps and flip-chip bonded using anisotropic conductive adhesive. Average contact resistances of the flip-chip joints were measured with respect to bonding pressure and presence of the CNT-Ag composite pads. When Cu/Sn chip bumps with CNT-Ag composite pads were flip-chip bonded to substrate Cu pads at 25MPa or 50 MPa, contact resistance was too high to measure. The specimen processed by flip-chip bonding the Cu/Sn chip bumps with CNT-Ag composite pads to the substrate Cu pads exhibited an average contact resistance of $213m{\Omega}$. On the other hand, the flip-chip specimens processed by bonding Cu/Sn chip bumps without CNT-Ag composite pads to substrate Cu pads at 25MPa, 50MPa, and 100MPa exhibited average contact resistances of $370m{\Omega}$, $372m{\Omega}$, and $112m{\Omega}$, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.9-15
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• 2008

Microstructure and contact resistance of the Au-Sn solder joints were characterized after flip-chip bonding of the Au/Sn bumps processed by successive electrodeposition of Au and Sn. Microstructure of the Au-Sn solder joints, formed by flip-chip bonding at $285^{\circ}C$ for 30 sec, was composed of the $Au_5Sn$+AuSn lamellar structure. The interlamellar spacing of the $Au_5Sn$+AuSn structure increased by reflowing at $310^{\circ}C$ for 3 min after flip-chip bonding. While the Au-Sn solder joints formed by flip-chip bonding at $285^{\circ}C$ for 30 sec exhibited an average contact resistance of 15.6 $m{\Omega}$/bump, the Au-Sn solder joints reflowed at $310^{\circ}C$ for 3 min after flip-chip bonding possessed an average contact resistance of 15.0 $m{\Omega}$/bump.

• Composites Research
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• v.36 no.6
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• pp.422-428
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• 2023

The electrical contact resistance between the bipolar plate (BP) and the carbon felt electrode (CFE), which are in contact by the stack clamping pressure, has a great impact on the stack efficiency because of the relatively low clamping pressure of the vanadium redox flow battery (VRFB) stack. In this study, a polyethylene (PE) composite-CFE hybrid bipolar plate structure is developed through a local heat welding process to reduce such contact resistance and improve cell performance. The PE matrix of the carbon fiber composite BP is locally melted to create a direct contact structure between the carbon fibers of CFE and the carbon fibers of BP, thereby reducing the electrical contact resistance. Area specific resistance (ASR) and gas permeability are measured to evaluate the performance of the PE composite-CFE hybrid bipolar plate. In addition, an acid aging test is performed to measure stack reliability. Finally, a VFRB unit cell charge/discharge test is performed to compare and analyze the performance of the developed PE composite-CFE hybrid BP and the conventional BP.