• Journal of Power Electronics
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• v.17 no.4
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• pp.1109-1116
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• 2017

Wireless power transfer (WPT) technology has the advantages of intelligence and facilitation. This paper designs a WPT system applied to battery charging and provides a strategy which switches from the constant current (CC) charging mode to constant voltage (CV) charging mode. The LCL-LCL topology is used to realize the CC output, while the LCL-S (series compensation) topology is used to realize the CV output. The main factor affecting the output characteristics is extracted by analyzing the two topologies above. Based on the main factor, this paper puts forward a modified way to design the system. In addition, on-line monitors for the battery and switches are placed at receiving side, which avoids the need for introducing an information interaction module into the system. Therefore, the complexity of the controlling system is reduced. Finally, simulation and experimental analyses are carried out to verify the correctness of the compound topologies.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.106-117
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• 2022

Multiple output converters can be utilized when various output voltages are required in applications. Recently, one of the multiple output converters called fly-buck has been proposed, and has attracted attention due to the advantage that multiple output can be easily obtained with a simple structure. When constant on-time (COT) control is applied, the output ripple voltage must be treated carefully for control stability and voltage regulation characteristics in consideration of the inherent energy transfer characteristics of the fly-buck converter. This study analyzes the operation principle of the fly-buck converter with a ripple generation network and presents the design guideline for the improved output voltage regulation. Validity of the analysis and design guideline is verified using a 5 W prototype of the COT controlled fly-buck converter with a ripple generation network for telecommunication auxiliary power supply.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.10
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• pp.2028-2037
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• 2009

This paper presents the simulator for dynamic modeling of a MT(micro turbine) during start-up period. The simulator is implemented by modeling a dynamic power of main components of a MT including compressor, combustor and turbine. A modeling for a MT under steady state operation can be accurately built from thermodynamics analysis. But dynamic modeling during start-up period is very difficult because efficiency of main components is very low and the designed value has big error and nonlinear characteristics during start-up. In this paper, new method without using thermodynamics analysis during start-up is proposed for the simulator. The power models of main components are derived from analysis of the experimental operation data by test motoring using a electric starter under constant power output. The simulator is developed using MATLAB/Simulink. For constant power output control, sensorless vector inverter is designed and algorithms for starting from stall and method for controling a output power are proposed. The performance of developed simulator is verified by comparing experimental and simulation start-up results.

• Journal of Power Electronics
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• v.18 no.2
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• pp.533-546
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• 2018

This study proposes a comprehensive mathematical model that includes coil-system circuit and loss models for power converters in wireless power transfer (WPT) systems. The proposed model helps in understanding the performance of WPT systems in terms of coil-to-coil efficiency, overall efficiency, and output power capacity and facilitates system performance optimization. Three methods to achieve constant output power for variable-load systems are presented based on system performance analysis. An optimal method can be selected for a specific WPT system by comparing the efficiencies of the three methods calculated with the proposed model. A two-coil 1 kW WPT system is built to verify the proposed mathematical model and constant output power control methods. Experimental results show that when the load resistance varies between 5 and $25{\Omega}$, the system output power can be maintained at 1 kW with a maximum error of 6.75% and an average error of 4%. Coil-to-coil and overall efficiencies can be maintained at above 90% and 85%, respectively, with the selected optimal control method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.457-458
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• 2008

This paper presents an output common mode current compensation method to achieve both constant Gm and constant gain. A conventional rail-to-rail CMOS op-amp with constant Gm was designed by using complementary differential input stage and current compensation skills. But it doesn't operate constant gain, because of output resistance variation. With $0.18{\mu}m$ CMOS process, the simulation results show that the differential gain variation can achieve less than 1.3dB. And a 60dB gain, a 13.5MHz unity gain-frequency, and 1mW power consumption, when operating at 1.8V and 10pF load.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.281-284
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• 2003

Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.748-751
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• 2000

in this paper the design procedure of three phase voltage source inverter output filter is described. The 'd' axis transfer function of the filter output voltage to the load current is described with the capacitor value and the system time constant including the controller. This means that the relation between the filter capacitor value and the system time constant is given as the closed form. By using the above closed form the capacitor value can be calculated with the system time constant is given as the closed,. form the capacitor value can be calculated with the system time constant which can be implemented practically not using the try and error method. And as the effect of the load is connected.

• Journal of Power Electronics
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• v.16 no.3
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• pp.840-848
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• 2016

A primary-side regulation AC-DC converter operating in the PFM (Pulse Frequency Modulation) mode with a high precision output current is designed, which applies a novel inductance compensation technique to improve the precision of the output current, which reduces the bad impact of the large tolerance of the transformer primary side inductance in the same batch. In this paper, the output current is regulated by the OSC charging current, which is controlled by a CC (constant current) controller. Meanwhile, for different primary inductors, the inductance compensation module adjusts the OSC charging current finely to improve the accuracy of the output current. The operation principle and design of the CC controller and the inductance compensation module are analyzed and illustrated herein. The control chip is implemented based on a TSMC 0.35μm 5V/40V BCD process, and a 12V/1.1A prototype has been built to verify the proposed control method. The deviation of the output current is within ±3% and the variation of the output current is less than 1% when the inductances of the primary windings vary by 10%.