• 제목/요약/키워드: communication architecture

검색결과 2,642건 처리시간 0.033초

UWB OFDM 통신 시스템 용 FFT(Fast Fourier Transform) 설계에 관한 연구 (A Study on the Design of FFT Architecture for Ultra-Wide Band OFDM Communication System)

  • 박계완;윤상훈;정정화
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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    • pp.309-312
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    • 2004
  • This paper proposes the architecture of UWB OFDM communication system. More high data rate is requested in the 128-point FFT/IFFT of the UWB OFDM communication system than the conventional communication systems. So, the proposed architecture uses pipeline and parallel architecture. For a highly efficient architecture, the optimal clipping power and the input quantization bits are found in simulation. The hardware complexity of the proposed architecture is presented is consideration of Adder, Register and Complex Multiplier.

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영화를 활용한 건축 및 의사소통의 융합 교육 방법 - 다큐멘터리 <말하는 건축가>를 중심으로 - (The Research on Convergence Education Method of Architecture and Communication Using Film - Focused , a Documentary Film -)

  • 남진숙;변나향
    • 공학교육연구
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    • 제18권6호
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    • pp.70-79
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    • 2015
  • This paper proposes a convergence education method that combines architecture and communication through a documentary film entitled the Talking Architecture. The purpose of this program is to propose a new teaching and learning method for architecture education and investigates what would be an effective method of communication for architects. As mentioned above, this paper proposes a teaching method and a model applicable to actual classes based on the Talking Architect. It is proved that the method can be used for various types of classes and fields such as architectural expression, architectural planning and designing, housing theory, building structure, building materials, and other subject matters. In addition, this paper explores how architects communicate as described in the film. The findings show the potential of integrity, negotiating capability, and the convergent method of thinking and communication between the humanities and architecture as a positive communication model for architects. This paper opens up the possibilities for convergence education in the field of engineering education through three key words: film, architecture, and communication. And this paper is worth in that it is a useful method for developing convergence courses and team-teaching courses.

진화 하드웨어 시스템을 위한 재구성 가능한 디지털 신호처리 구조 (A Reconfigurable Digital Signal Processing Architecture for the Evolvable Hardware System)

  • 이한호;최창석;이용민;최진택;이종호;정덕진
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2006년도 하계종합학술대회
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    • pp.663-664
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    • 2006
  • This paper presents a reconfigurable digital signal processing(rDSP) architecture that is effective for implementing adaptive digital signal processing in the applications of smart health care system. This rDSP architecture employs an evolution capability of FIR filters using genetic algorithm. Parallel genetic algorithm based rDSP architecture evolves FIR filters to explore optimal configuration of filter combination, associated parameters, and structure of feature space adaptively to noisy environments for an adaptive signal processing. The proposed DSP architecture is implemented using Xilinx Virtex4 FPGA device and SMIC 0.18um CMOS Technology.

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Empirical Performance Evaluation of Communication Libraries for Multi-GPU based Distributed Deep Learning in a Container Environment

  • Choi, HyeonSeong;Kim, Youngrang;Lee, Jaehwan;Kim, Yoonhee
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제15권3호
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    • pp.911-931
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    • 2021
  • Recently, most cloud services use Docker container environment to provide their services. However, there are no researches to evaluate the performance of communication libraries for multi-GPU based distributed deep learning in a Docker container environment. In this paper, we propose an efficient communication architecture for multi-GPU based deep learning in a Docker container environment by evaluating the performances of various communication libraries. We compare the performances of the parameter server architecture and the All-reduce architecture, which are typical distributed deep learning architectures. Further, we analyze the performances of two separate multi-GPU resource allocation policies - allocating a single GPU to each Docker container and allocating multiple GPUs to each Docker container. We also experiment with the scalability of collective communication by increasing the number of GPUs from one to four. Through experiments, we compare OpenMPI and MPICH, which are representative open source MPI libraries, and NCCL, which is NVIDIA's collective communication library for the multi-GPU setting. In the parameter server architecture, we show that using CUDA-aware OpenMPI with multi-GPU per Docker container environment reduces communication latency by up to 75%. Also, we show that using NCCL in All-reduce architecture reduces communication latency by up to 93% compared to other libraries.

DF-DPD의 고속 데이터 처리 구조 (Architecture for High-speed Data Processing of DF-DPD)

  • 김영삼;정진두;윤상훈;장성현;정만희;오대건;정정화
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.373-374
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    • 2008
  • This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.

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Low-Power Bus Architecture Composition for AMBA AXI

  • Na, Sang-Kwon;Yang, Sung;Kyung, Chong-Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제9권2호
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    • pp.75-79
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    • 2009
  • A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

Intelligent Hybrid Modular Architecture for Multi Agent System

  • Lee, Dong-Hun;Baek, Seung-Min;Kuc, Tae-Yong;Chung, Chae-Wook
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2004년도 ICCAS
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    • pp.896-902
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    • 2004
  • The purpose of the study of multi-robot system is to realize multi-robot system easy for the control of robot system in case robot is adapted in the complicated environment of task structure. The purpose of the study of multi-robot system is to realize multi-robot system easy for the control of robot system in case robot is adapted in the complicated environment of task structure. To make real time control possible by making effective use of recognized information in this dynamic environment, suitable distribution of tasks should be made in consideration of function and role of each performing robots. In this paper, IHMA (Intelligent Hybrid Modular Architecture) of Intelligent combined control architecture which utilizes the merits of deliberative and reactive controllers will be suggested and its efficiency will be evaluated through the adaptation of control architecture to representative multi-robot system.

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The Implementation of EIA 709.1 Standard Protocol Based Home Control System Architecture having Network Configuration Function

  • Lee, Chang-Eun;Park, June-Hee;Son, Young-Sung;Moon, Kyeung-Deok
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -1
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    • pp.560-563
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    • 2002
  • This paper proposes a home control system architecture that have network configuration function. The proposed home control system architecture is implemented with partly hardware and software. For implementation of this system architecture, we developed ECONICS which is home automation controller. ECONICS consists of main board and communication modem. This communication modem supply the power line communication. The physical layer and the MAC layer software of EIA 709.1 standard protocol are implemented in communication modem. The upper layer software of EIA 709.1 standard protocol and home configuration software for home network installation, management, diagnostics, control and monitoring are implemented in main board of ECONICS. We verified the commercial feasibility of the proposed system through the home network configuration and operation. As a result, we have concluded that the proposed home control system architecture provides all the key function necessary to easily manage and control home network nodes.

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Bridging the Gap: Follow-up Strategies for Effective Software Architecture Implementation

  • Abdullah A H Alzahrani
    • International Journal of Computer Science & Network Security
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    • 제24권7호
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    • pp.1-10
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    • 2024
  • Software architecture are High-level design decisions shaping a software system's components, structure, and interactions. It can be a blueprint for development, evolution, and ongoing maintenance. This research investigates the communication practices employed by software architects and developers to ensure adherence to the designed software architecture. It explores the factors influencing the selection of follow-up methods and the impact of follow-up frequency on successful implementation. Findings reveal that formalized follow-up procedures are not yet a ubiquitous element within the software development lifecycle. While electronic communication, particularly email, appears to be the preferred method for both architects and developers, physical and online meetings are utilized less frequently. Interestingly, the study suggests a potential confidence gap, with architects expressing concerns about developers' ability to faithfully implement the architecture. This may lead to architects providing additional clarification. Conversely, while most developers reported confidence in their software knowledge, overly detailed architecture documentation may pose challenges, highlighting the need for architects to consider alternative communication strategies. A key limitation of this study is the sample size, restricting the generalizability of the conclusions. However, the research offers valuable preliminary insights into the communication practices employed for architecture implementation, paving the way for further investigation with a larger and more diverse participant pool.

An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding

  • Jin, Xianzhe;Ryoo, Kwangki
    • Journal of information and communication convergence engineering
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    • 제11권2호
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    • pp.118-123
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    • 2013
  • This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.