• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.865-868
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• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.78-84
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• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.356-359
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• 1999

A high performance 16bit multiplier for asynchronous systems has been designed using asynchronous design methodology. The 4-radix modified Booth algorithm, TSPC (true single phase clocking) registers, and modified 4-2 counters using DPTL (differential pass transistor logic) have been used in our multiplier. It is implemented in 0.65${\mu}{\textrm}{m}$ double-poly/double-metal CMOS technology by using 6616 transistors with core size of 1.4$\times$1.1$\textrm{mm}^2$. And our design results in a computation rate exceeding 60MHz at a supply voltage of 3.3V.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.5
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• pp.23-30
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• 1983

A new runlength-limited minimum-bandwidth line code is designed by modifying the duobinary code. Since the new code is runlength limited, the need for a data scrambling before transmission is eliminated. The eye width and the error probability of the new code are shown to be almost the same as those of the duobinary code. Also, the power spectral shape is scarcely changed, so that the new code is suitable for such low-pass channels as optical fibers.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.199-204
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• 2007

This paper presents design of interleave configured dc-dc converter for high power distributed power system applications. The multi channel interleaving buck converter with small inductance has proved to be suitable for micro-grid, requiring medium output voltages, high output currents and fast transient response. Integrated magnetic components are used to reduce the size of the converter and improve efficiency. Unlike conventional methods, the distributed approach requires no centralized control, automatically accommodates varying numbers of converter cells, and is highly tolerant of subsystem failures. A general methodology for achieving distributed interleaving is proposed, along with a specific implementation approach. The design and simulation verification of switching frequency 10 kHz system is presented with interleaved clocking of the converter cells. The simulation (simulated by PSIM 6.1) results corroborate the analytical predictions and demonstrate the tremendous benefits of the distributed interleaving approach.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.