• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.12A
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• pp.1128-1135
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• 2010

A wireless positioning system using ultra-wideband (UWB) for indoor wireless positioning uses ranging data in order to accurately estimate location. Commonly, ranging uses time of arrival (TOA), time difference of arrival (TDOA) based on arrival time. The most fundamental issue in the ranging for wireless positioning is to obtain clock synchronization among the sensor nodes and to correct an error caused by the relative clock offset from each node. In this paper, we propose ranging and positioning technique using common clock in order to solve both clock synchronization and clock offset problems. To verify the performance of proposed, we simulated ranging and positioning in channel model introduced by IEEE 802.15.4a Task Group and then results show that location estimation is unaffected by clock offset.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.395-400
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• 2006

Among the various error sources in positioning and navigation, the paper focuses on the modeling and prediction of receiver clock bias and then tries to achieve positioning based on simulated and predicted clock bias. With the SA off, it is possible to model receiver clock bias more accurately. We selected several types of GNSS receivers for test using ARMA model. To facilitate prediction with short and limited sample pseudorange observations, AR and ARMA are compared, and the improved AR model is presented to model and predict receiver clock bias based on previous solutions. Our work extends to clock bias prediction and positioning based on predicted clock bias using only 3 satellites that is usually the case under urban canyon situation. In contrast to previous experiences, we find that a receiver clock bias can be well modeled using adopted ARMA model. Test has been done on various types of GNSS receivers to show the validation of developed model. To further develop this work, we compare solution conditions in terms of DOP values when point positioning is conducted using 3 satellites to simulate urban positioning environment. When condition allows, height component is derived from other ways and can be set as known values. Given this condition, location is possible using less than 2 GNSS satellites with fixed height. Solution condition is also discussed for this background using mode of constrained positioning. We finally suggest an effective predictive time span based on our test exploration under varied conditions.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.227-236
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• 2005

We study, in terms of VoIP user assessment of voice quality, the synchronization of measurement system is important. Commonly the synchronization system uses NTP(Network Time Protocol) or GPS(Global Positioning System), these synchronization method has time error of distance, system overhead of data processing, and system specialized clock error. we propose and implement the synchronization method to correct time error between two measurement system in the internet. So the time synchronization of systems can get time error, then user assessment of voice quality become reliable.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.9
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• pp.871-877
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• 2012

An error analysis of PPP (Precise Point Positioning) using IF (Ionosphere Free) combination is given in this paper. It is shown that the performance of the ordinary model with positions, clock bias, integer ambiguities and ionosphere delay as unknowns is equivalent to that of an ionosphere difference combination where ionosphere delay is cancelled out. Furthermore, it is shown that IF combination is an ionosphere difference combination but not unique. It is also proved that all difference models show same performances. The error analysis evaluated with a hardware simulator and real measurements show that the ionosphere delay is effectively eliminated by IF combination or equivalently by the ionosphere difference combination. However, if bias errors such as troposphere, clock bias or multipath are included in the measurements, the performance of the IF combination is degraded because the bias errors are amplified by the ionosphere difference operation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9A
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• pp.868-877
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• 2006

Sensor network applications need synchronized time to the highest degree such as object tracking, consistent state updates, duplicate detection, and temporal order delivery. In addition, reliability issues and fault tolerance in sophisticated sensor networks have become a critical area of research today. In this paper, we proposed a fault tolerant clock management scheme in sensor networks considering two cases of fault model such as network faults and clock faults. The proposed scheme restricts the propagation of synchronization error when there are clock faults of nodes such as rapid fluctuation, severe changes in drift rate, and so on. In addition, it handles topology changes. Simulation results show that the proposed method has about $1.5{\sim}2.0$ times better performance than TPSN in the presence of faults.