ETRI Journal
- Volume 30 Issue 2
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- Pages.268-274
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- 2008
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- 1225-6463(pISSN)
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- 2233-7326(eISSN)
Design and Implementation of Open-Loop Clock Recovery Circuit for 39.8 Gb/s and 42.8 Gb/s Dual-Mode Operation
- Lim, Sang-Kyu (IT Convergence Technology Research Laboratory, ETRI) ;
- Cho, Hyun-Woo (Broadcasting & Telecommunications Convergence Research Laboratory, ETRI) ;
- Shin, Jong-Yoon (Optical Communications Research Center, ETRI) ;
- Ko, Je-Soo (Optical Communications Research Center, ETRI)
- Received : 2007.08.22
- Published : 2008.04.30
Abstract
This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of
Keywords
- Clock recovery circuit;
- clock and data recovery;
- CDR;
- open-loop clock recovery;
- 40 Gb/s optical transmission system