• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.05a
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• pp.187-190
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• 2000

Chua's circuit is a simple electronic network which exhibits a variety of bifurcation and attractors. The circuit consists of two capacitors, an inductor, a linear resistor, and a nonlinear resistor. In this paper, a transmitter and a receiver using two identical Chua's circuits are proposed and synchronizations of a power line are investigated. Since the synchronization of the power line system is impossible by coupled synchronization, theory having both the drive-response and the coupled synchronization is proposed. As a result, the chaos synchronization has delay characteristics in the power line transmission system caused by the line parameters L and C.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.10a
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• pp.272-277
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• 1999

The necessity of voice recording device was increased using voice signal IC with designed LSI/VLSI. The control unit which developed here voice recorder has low power dissipation, portable, and comfortable using voice source. However, the Korea voice recorder abilities far behind of foreign products for its performance and size on sailing. So we used Chua circuit to improvement voice quality abilities after minimize power supply device and circuit by designing voice recording device into lower power dissipation power circuit.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.1789-1794
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• 2014

This paper suggests an application method for a superconducting fault current limiter (SFCL) using an evaluation index to estimate the risk regarding the short-circuit capacity of the circuit breaker (CB). Recently, power distribution systems have become more complex to ensure that supply continuously keeps pace with the growth of demand. However, the mesh or loop network power systems suffer from a problem in which the fault current exceeds the short-circuit capacity of the CBs when a fault occurs. Most case studies on the application of the SFCL have focused on its development and performance in limiting fault current. In this study, an analysis of the application method of an SFCL considering the risk of the CB's short-circuit capacitor was carried out in situations when a fault occurs in a loop network power system, where each line connected with the fault point carries a different current that is above or below the short-circuit capacitor of the CB. A loop network power system using PSCAD/EMTDC was modeled to investigate the risk ratio of the CB and the effect of the SFCL on the reduction of fault current through various case studies. Through the risk evaluations of the simulation results, the estimation of the risk ratio is adequate to apply the SFCL and demonstrate the fault current limiting effect.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.6
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• pp.543-550
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• 2006

A three-level sustain circuit with six-switches for an ac plasma display panel (AC-PDP) drive is proposed. The proposed circuit features half the voltage stresses of sustain switches and clamp diodes and significantly reduced power losses compared with those of the conventional ones. This circuit, realizable with reduced cost of the semiconductor devices, gives a significant improvement in the power efficiency, essential for the design of a drive circuit for the AC-PDP. A comparative analysis and experimental results we presented to show the validity of the proposed sustainer circuit.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.1
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• pp.41-48
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• 2003

In this paper, a new equivalent circuit for a defected ground structure(DGS) is proposed and adapted to design of a power amplifier for performance improvement. The DGS equivalent circuit presented in this paper consists of parallel LC resonator and parallel capacitance to describe the fringing fields due to the etched defects on the metallic ground plane, and also is used to optimize the matching circuit of a power amplifier. A previous research has also used a DGS for harmonic rejection and efficiency improvement of a power amplifier(1), however, there was no exact equivalent circuit analysis. In this paper, we suggest a novel design method and show the performance improvement of a class AB power amplifier by using the equivalent circuit of a DGS applied to output matching circuit. The design method presented in this paper can provide very accurate design results to satisfy the optimum load condition and the desirable harmonic rejection, simultaneously. As a design example, we have designed a 20W power amplifier with and without circuit simulation of DGS, and compared the measurement results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.141-146
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• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.385-388
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• 1999

A new frequency-variant equivalent circuit model of power/ground plane is presented. The equivalent circuit is modeled with grid cells. The circuit parameters of each cell were extracted by using Fasthenry. To verify the developed circuit model, its s-parameters are compared with the measured s-parameters 〔2〕 and the full-wave simulation-based s-parameters. Consequently, it is shown that our frequency-variant equivalent circuit model can accurately predict imperfect ground effects under the high frequency operation of electronic package.

• Journal of electromagnetic engineering and science
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• v.17 no.2
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• pp.105-107
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• 2017

The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.5
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• pp.431-439
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• 2006

This paper proposes a new commutation circuit for a PWM Cuk AC-AC converter. The proposed commutation circuit utilizes a modified Undeland snubber as a commutation aid. The snubber circuit has some good features such as reduction of voltage/current stress of the main switches and improved efficiency. The experiment results show the adaptability and feasibility of the proposed commutation circuit.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.