• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.940-943
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• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.59-66
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• 1997

Neural networks has widely been be used for several practical applications such as speech, image processing, and pattern recognition. Thus, a approach to the voltage-controlled current source in areas of neural networks, the key features of CNN in locally connected only to its netighbors. Because the architecture of the interconnection elements between cells in very simple and space invariant, CNNs are suitable for VLSI implementation. In this paper, processing element of digital programmable CNN with variable template memory was implemented using CMOS circuit. CNN PE circuit was designe dto control gain for obtaining the optimal solutions in the CNN output. Performance of operation for 4*4 CNN circuit applied for fixed template and variable template analyzed with the result of simulation using HSPICE tool. As a result of simulations, the proposed variable template method verified to improve performance of operation in comparison with the fixed template method.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.837-840
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• 1999

In this paper, we design and verify the hardware circuit that performs PLCP(Physical Layer Convergence Protocol) protocol functions of physical layer in IEEE 802.11 frequency hopping WLAN(Wireless Local Area Network). Altera MAX＋PLUS I $I^{〔1〕}$ is used as a design tool. The designed circuit consists of control register module to interface with upper layer, FIFO module to transmit/receive data with upper layer, TX function module, and RX function module. It is verified that the developed circuit conforms well to the IEEE 802.11 standard specification and can support both 1Mbps and 2 Mbps transmission rate by simulation. The developed circuits can be utilized for the implementation of protocol processor in wireless LAN areas.

• Proceedings of the KSR Conference
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• 1998.05a
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• pp.408-418
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• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• Smart Media Journal
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• v.12 no.2
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• pp.83-90
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• 2023

The advent of quantum computers threatens the security of existing hash functions. In this paper, we confirmed the implementation results of quantum circuits for domestic/international hash functions, LSH, SHA2, SHA3 and SM3, and conducted a comparative analysis. To operate the existing hash function in a quantum computer, it must be implemented as a quantum circuit, and the quantum security strength can be confirmed by estimating the necessary quantum resources. We compared methods of quantum circuit implementation and results of quantum resource estimation in various aspects and discussed ways to meet quantum computer security in the future.

• Journal of Sensor Science and Technology
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• v.26 no.5
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• pp.331-337
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• 2017

A readout circuit for a tactile sensor pad based on force sensing resistors was proposed, which was composed of an analog signal conditioning circuit and a digital circuit with a microcontroller. The conventional signal conditioning circuit has a dc offset voltage in the output signal, which results from the reference voltage applied to the FSR devices. The offset voltage reduces the dynamic range of the circuit and makes it difficult to operate the circuit under a low voltage power supply. In the proposed signal conditioning circuit, the dc offset voltage was removed completely. The microcontroller with A/D converter and D/A converter was used to enlarge the measurement range of pressure. For this, the microcontroller adjusts the FSR reference voltage according to the resistance magnitude of FSR under pressure. The operation of the proposed readout circuit which was connected to a tactile sensor pad with $5{\times}10$ FSR array was verified experimentally. The experimental results show the proposed readout circuit has the wider measurement range of pressure than the conventional circuit. The proposed circuit is suitable for low voltage and low power applications.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.947-950
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• 1999

The PLD design of new scheme LCD driver circuit is described in this paper. A new scheme LCD driver circuit doesn't used microprocessor for the convenience of users. A new scheme LCD driver circuit consists of 4 main parts, that is, a serial/parallel communication control block part, a LCD controller part, a LCD driver part and a RAM/ROM control block part. The validity and efficiency of the proposed LCD driver circuit have been verified by simulation and by ALTERA EPM7192SQC160-15 PLD implementation in VHDL. After comparing this LCD driver circuit to specify it was verified that the developed LCD driver circuit showed has good performances, such as low cost, convenience of users.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Journal of information and communication convergence engineering
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• v.5 no.3
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• pp.285-288
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• 2007

PDP(Plasma Display Panel) driving circuit requires switching devices and capacitors to stand up high voltages over 150volts. Thereby the power consumption and the cost of a PDP driving circuit increase. In this paper, a PDP driving circuit is proposed that can be operated with a lower supply voltage than the supply voltage of conventional driving circuit. The operation of the proposed driving circuit is verified by the computer simulation and experiments. PSPICE simulation and experiments results show that the output signal can drive PDP cells when the supply voltage is higher than 40volts.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.12
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• pp.671-678
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• 2003

This paper proposes an expert system to generate automatically the test table of test system which can highly enhance the quality and productivity of product by inspecting quickly and accurately the defect device on the electronic circuit board tested. The expert system identifies accurately the tested components and the circuit patterns by tracing automatically the connectivity of circuit from electronic circuit database. And it generates automatically the test table to detect accurately the missing components, the misplaced components, and the wrong components for analog components such as resistance, coil, condenser, diode, and transistor, based on the experience knowledge of veteran expert. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. And, the validity of the builded expert system is proved by simulating for a typical electronic board model.