• Title/Summary/Keyword: circuit implementation

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Switching Function Implementation based on Graph (그래프에 기초한 스위칭함수 구현)

  • Park, Chun-Myoung
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.1965-1970
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    • 2011
  • This paper proposes the method of switching function implementation using switching function extraction based on graph over finite fields. After we deduce the matrix equation from path number of directional graph, we propose the switching function circuit algorithm, also we propose the code assignment algorithm for nodes which is satisfied the directional graph characteristics with designed circuits. We can implement more optimal switching function compare with former algorithm, also we can design the switching function circuit which have any natural number path through the proposed switching function circuit implementation algorithms. Also the proposed switching function implementation using graph theory over finite fields have decrement number of input-output, circuit construction simplification, increment arithmetic speed and decrement cost etc.

Implementation of Euclidean Calculation Circuit with Two-Way Addressing Method for Reed-Solomon Decoder (Reed-Solomon decoder를 위한 Two-way addressing 방식의 Euclid 계산용 회로설계)

  • Ryu, Jee-Ho;Lee, Seung-Jun
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.6
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    • pp.37-43
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    • 1999
  • Two-way addressing method has been proposed for efficient VLSI implementation of Euclidean calculation circuit for pipelined Reed-Solomon decoder. This new circuit is operating with single clock while exploiting maximum parallelism, and uses register addressing instead of register shifting to minimize the switching power. Logic synthesis shows the circuit with the new scheme takes 3,000 logic gates, which is about 40% reduction from the previous 5,000 gate implementation. Computer simulation also shows the power consumption is about 3mW. The previous implementation with multiple clock consumed about 5mW.

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A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation

  • Son, Hyeon-Sik;Moon, Byungin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.11 no.6
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    • pp.3208-3229
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    • 2017
  • Rectification is an essential procedure for simplifying the disparity extraction of stereo matching algorithms by removing vertical mismatches between left and right images. To support real-time stereo matching, studies have introduced several look-up table (LUT)- and computational logic (CL)-based rectification approaches. However, to support high-resolution images, the LUT-based approach requires considerable memory resources, and the CL-based approach requires numerous hardware resources for its circuit implementation. Thus, this paper proposes a multi-level accumulation-based rectification method as a simple CL-based method and its circuit implementation. The proposed method, which includes distortion correction, reduces addition operations by 29%, and removes multiplication operations by replacing the complex matrix computations and high-degree polynomial calculations of the conventional rectification with simple multi-level accumulations. The proposed rectification circuit can rectify $1,280{\times}720$ stereo images at a frame rate of 135 fps at a clock frequency of 125 MHz. Because the circuit is fully pipelined, it continuously generates a pair of left and right rectified pixels every cycle after 13-cycle latency plus initial image buffering time. Experimental results show that the proposed method requires significantly fewer hardware resources than the conventional method while the differences between the results of the proposed and conventional full rectifications are negligible.

Method and implementation for reducing stand by power consumption in SMPS with low-speedy power line communication (저속 전력선통신 적용 전원공급장치의 대기전력 절감 방법 및 구현)

  • Kim, Ki-Hyun;Son, Do-Sun;Kim, Hyoung-Woo;Seo, Kil-Soo;Kim, Sang-Cheol
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.1139-1140
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    • 2008
  • This paper is designated to introduce the method of reducing stand-by Power of SMPS applied PLC(Power Line Communication) and its implementation. PLC modem consists mainly of PLC Module, Coupling Circuit, ZCP(Zero-Cross Point) Circuit and Power Supply Circuit. By controlling power from Power Supply Circuit to PLC Module and ZCP Circuit, the reduction of Stand-by Power is established. When this method is applied to SMPS used for a low-speed PLC, about 50% power reduction is provided, compared to the other case to which it is not applied.

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A Study On Hardware Implementation of Canonical Chua's Circuit (Canonical Chua 회로의 Hardware 제작에 관한 연구)

  • Ko, Jae-Ho;Bang, Sung-Yun;Bae, Young-Chul;Yim, Hwa-Yeoung
    • Proceedings of the KIEE Conference
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    • 1997.07b
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    • pp.624-626
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    • 1997
  • Canonical Chua's circuit is a simple electronic circuit which exhibits a variety of bifurcation phenomena and attractors. It consists of two capacitors, an inductor, two linear resistors, and a nonlinear resistor. When the circuit exhibits chaotic signals, the nonlinear resistor of canonical Chua's circuit may have three different voltage - current characteristics. In this paper, the design methodology for practical implementation of the nonlinear resistors which have all these characteristics is described. In addition, the effectiveness of result is shown by not only the MATLAB simulation but also the PSPICE simulation.

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Design and Implementation of a Adapted Genetic Algorithm for Circuit Placement (어댑티드 회로 배치 유전자 알고리즘의 설계와 구현)

  • Song, Ho-Jeong;Kim, Hyun-Gi
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.17 no.2
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    • pp.13-20
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    • 2021
  • Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

SoftMax Computation in CNN Using Input Maximum Value (CNN에서 입력 최댓값을 이용한 SoftMax 연산 기법)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.2
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    • pp.325-328
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    • 2022
  • A convolutional neural network(CNN) is widely used in the computer vision tasks, but its computing power requirement needs a design of a special circuit. Most of the computations in a CNN can be implemented efficiently in a digital circuit, but the SoftMax layer has operations unsuitable for circuit implementation, which are exponential and logarithmic functions. This paper proposes a new method to integrate the exponential and logarithmic tables of the conventional circuits into a single table. The proposed structure accesses a look-up table (LUT) only with a few maximum values, and the LUT has the result value directly. Our proposed method significantly reduces the space complexity of the SoftMax layer circuit implementation. But our resulting circuit is comparable to the original baseline with small degradation in precision.

Practical Design and Implementation of a Power Factor Correction Valley-Fill Flyback Converter with Reduced DC Link Capacitor Volume (저감된 DC Link Capacitor 부피를 가지는 역률 개선 Valley-Fill Flyback 컨버터의 설계 및 구현)

  • Kim, Se-Min;Kang, Kyung-Soo;Kong, Sung-Jae;Yoo, Hye-Mi;Roh, Chung-Wook
    • The Transactions of the Korean Institute of Power Electronics
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    • v.22 no.4
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    • pp.277-284
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    • 2017
  • For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

Surface EMG Network Analysis and Robotic Arm Control Implementation

  • Ryu, Kwang-Ryol
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.743-746
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    • 2011
  • An implementation for surface EMG network analysis and vertical control system of robotic arm is presented in this paper. The transmembranes are simulated by equivalent circuit and cable equation for propagation to be converted to circuit networks. The implementation is realized to be derived from the detecting EMG signal from 3 electrodes, and EMG transmembrane signals of human arm muscles are detected by several surface electrodes, high performance amplifier and filtering, converting analog to digital data and driving a servomotor for spontaneous robotic arm. The system is experimented by monitoring multiple steps vertical control angles corresponding to biceps muscle movement. The experimental results are that the vertical moving control level is measured to around 2 degrees and mean error ranges are lower 5%.

An Implementation of Driving Circuit for Resistive Touch Panel (저항막식 터치 패널의 구동회로 제작)

  • Han, Hyung-Seok
    • Journal of The Institute of Information and Telecommunication Facilities Engineering
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    • v.8 no.1
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    • pp.36-39
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    • 2009
  • In this paper, we propose a 4-wire type driving circuit for resistive touch panel which was manufactured at the lab. The circuit is designed by using the touch panel controller ADS7846 and AVR microcontroller board. The test result shows that the designed circuit can give and transmit the position information of touch panel to the computer.

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