The Transactions of the Korean Institute of Power Electronics (전력전자학회논문지)

The Korean Institute of Power Electronics (전력전자학회)
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Practical Design and Implementation of a Power Factor Correction Valley-Fill Flyback Converter with Reduced DC Link Capacitor Volume

저감된 DC Link Capacitor 부피를 가지는 역률 개선 Valley-Fill Flyback 컨버터의 설계 및 구현

  • Received : 2016.12.20
  • Accepted : 2017.03.27
  • Published : 2017.08.20
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Abstract

For passive power factor correction, the valley fill circuit approach is attractive for low power applications because of low cost, high efficiency, and simple circuit design. However, to vouch for the product quality, two dc-link capacitors in the valley fill circuit should be selected to withstand the peak rectified ac input voltage. The common mode (CM) and differential mode (DM) choke should be used to suppress the electromagnetic interference (EMI) noise, thereby resulting in large size volume product. This paper presents the practical design and implementation of a valley fill flyback converter with reduced dc link capacitors and EMI magnetic volumes. By using the proposed over voltage protection circuit, dc-link capacitors in the valley fill circuit can be selected to withstand half the peak rectified ac input voltage, and the proposed CM/DM choke can be successfully adopted. The proposed circuit effectiveness is shown by simulation and experimentally verified by a 78W prototype.

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References

  1. P. Parto and K. Smedley, "Passive PFC for flyback converters," PCIM 99, Chicago, 1999.
  2. M. H. Kheraluwala and S. A. El-Hamamsy, "Modified valley fill high factor electronic ballast for compact fluorescent lamps," in Proc. IEEE Power Electronics Specialists Conference, pp. 10-14, Aug. 2002.
  3. J. Lam and P. K. Jain, "A new passive valley fill dimming electronic ballast with extended line current conduction angle," Telecommunications Energy Conference, 11-3, Sep. 2006.
  4. K. K. Sum, "Valley-fill power factor correction circuit," U.S. Patent 6,141,230, Oct. 31, 2000.
  5. N. Y. Choi, C. G. Ahn, and C, H. Lee, "A new valley-fill circuit for improving power factor," The Institute of Electronics Engineers of Korea Annual Conference, Vol. 26, No. 1, pp. 2935-2938, Jul. 2003.
  6. N. Y. Choi and C. H. Lee, "Current THD improvement of valley-fill rectifier," Journal of the Korean Institute of Illuminating and Electrical Installation Engineers, Vol. 22, No. 1, pp. 87-94, Jan. 2008. https://doi.org/10.5207/JIEIE.2008.22.1.087
  7. S. M. Kim, S. Y. Kim, S. J. Kong, K. S. Kang, and C. W. Roh, "Practical design and implementation of valley-fill flyback converter having power factor correction," the Korean Institute of Power Electronics Annual Conference, pp. 225-226, Jul. 2016.
  8. J. J Ko, J. H. Choi, S. K. Kim, J. J. Park, D. Y. Cho, and C. W. Roh, "Reactor design using the leakage inductances of CM choke," the Korean Institute of Power Electronics Annual Conference, pp. 277-278, Jul. 2012.
  9. B. S. Kim, S. E. Kim, K. S. Kang, and C. W. Roh, "Application of reduced inductor for interleaved PFC converter," The Korean Institute of Power Electronics Annual Conference, pp. 339-340, Jul. 2013.
  10. R. W. Erickson and D. Maksimovic, "Fundamentals of power electronics," Second Edition, Kluwer Academic Publishers, pp. 121-181, 2000.