• Title/Summary/Keyword: circuit

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A Study on A Gas Circuit Breaker Development Using Simplified Synthetic Testing Facility (간이합성시험설비를 이용한 가스차단기 개발에 관한 연구)

  • Chong, Jin-Kyo;Kim, Gyu-Tak
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.902-904
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    • 2007
  • A $SF_6$ gas circuit breakers are widely used for short circuit current interruption in EHV or UHV power system. During a $SF_6$ gas circuit breaker development, Simplified synthetic testing facility is used. This paper shows how simplified synthetic testing facility is used for a SF6 gas circuit breaker development.

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The Relay Circuit to EMFG Conversion with a Box´s Characteristic Equation

  • Goo, Paek-Hyung;Mo, Yeo-Jeong
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.60.5-60
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    • 2001
  • It is very difficult to design and analyze the relay circuit because one have to consider and analyze in order the behavior in which the relay contacts. In this paper, we propose the relay circuit to EMPG (Extended Mark Flow Graph) convension with a box´s characteristic equation. It will give you a lot of benefits in case of analysis and check of the relay circuit to convert the relay circuit into EMPG.

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Study on the Operating Characteristics of High Voltage Impulse Track Circuit (고전압 임펄스궤도회로의 동작특성 연구)

  • Lee, Tae-Hoon;Park, Ki-Bum;Jeon, Yong-Joo;Ryu, Young-Tae
    • Proceedings of the KSR Conference
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    • 2008.11b
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    • pp.1279-1284
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    • 2008
  • This paper presents the operating characteristic of high voltage impulse(HVI) track circuit owing to the ill-contact of impedance bond lead wire. The characteristic operations of the track include rail voltage and current. Measurements are carried out using oscilloscope with current probe and it analyzed the abnormal operation due to connector of protective wire. Finally, suitable track circuit is proposed for conventional line, and operating characteristic of HVI track circuit is affected by bypass circuit.

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SOME PROBLEMS AND RESULTS ON CIRCUIT GRAPHS AND TRIANGULAR GRAPHS

  • Jung, Hwan-Ok
    • Journal of applied mathematics & informatics
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    • v.26 no.3_4
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    • pp.531-540
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    • 2008
  • We discuss the decomposition problems on circuit graphs and triangular graphs, and show how they can be applied to obtain results on spanning trees or hamiltonian cycles. We also prove that every circuit graph containing no separating 3-cycles can be extended by adding new edges to a triangular graph containing no separating 3-cycles.

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Three Phase GTO PWM Inverter Using the Energy Recovery Snubber Circuit (에너지 회생 방식 스너버 회로를 각는 3상 GTO PWM 인버터)

  • 신병철;강경호;차재현;차득근;김명현
    • Proceedings of the KIPE Conference
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    • 1998.07a
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    • pp.255-259
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    • 1998
  • This paper is proposed three phase GTO PWM Inverter with energy recovery snubber circuit. The proposed energy recovery snubber circuit effective in reduction of the power loss in the Inverter system than asymmetry GTO snubber circuit.

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Analysis and Remedy of TFT Based Current Mode Logic Circuit Performance Degradation due to Device Parameter Fluctuation

  • Lee, Joon-Chang;Jeong, Ju-Young
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.535-538
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    • 2005
  • We report the influence of the threshold voltage and mobility fluctuation in TFT on current mode digital circuit performance. We found that the threshold voltage showed more serious circuit malfunction. We studied new circuit configuration for improvement.

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Low Cost Circuit Design for a Sentence Speech Recognition (저가의 단 문장 음성 인식회로 설계)

  • 최지혁;홍광석
    • Proceedings of the IEEK Conference
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    • 2002.06d
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    • pp.365-368
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    • 2002
  • In this paper, we present a low cost circuit design for a sentence speech recognition. The basic circuit of the designed sentence speech recognizer is composed of resistor, capacitance, OP Amp, counter and logic gates. Through a sentence recognition experiment, we can find the effectiveness of the designed sentence recognition circuit

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Analysis of Operation Characteristics of DC Circuit Breaker with Superconducting Current Limiting Element (초전도 전류제한소자를 적용한 DC 차단기의 동작 특성 분석)

  • Jung, Byung-Ik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.15 no.6
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    • pp.1069-1074
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    • 2020
  • Since DC has no zero point, an arc occurs when the DC circuit breaker performs a shutdown operation. In this case, a fatal accident may occur in the circuit breaker or in the grid, depending on the magnitude of the arc. Therefore, the shutdown performance and the reliability of the circuit breaker are important in the commercialization of HVDC. In this study, a superconducting LC circuit breaker was proposed to improve the performance and the reliability of the DC circuit breaker. The superconducting LC circuit breaker applied a superconducting coil to the inductor of the existing LC circuit breaker. Other than limiting the initial fault current, it also creates a stable zero point in the event of a fault current. To verify this, simulation was performed through EMTDC/PSCAD. Furthermore, the superconducting LC circuit breaker was compared with the LC circuit breaker with a normal coil. As a result, it was found that the LC circuit breaker with the superconducting coil limited the initial fault current further by approximately 12 kA compared to the LC circuit breaker with a normal coil. This reduced the arc extinguish time by approximately 0.16 sec, thereby decreasing the elctrical power burden on the circuit breaker.

Sensing scheme of current-mode MRAM (전류 방식 MRAM의 데이터 감지 기법)

  • Kim Bumsoo;Cho Chung-Hyung;Hwang Won Seok;Ko Ju Hyun;Kim Dong Myong;Min Kyeong-Sik;Kim Daejeong
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.419-422
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    • 2004
  • A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

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Design of a Low-Power MOS Current-Mode Logic Parallel Multiplier (저 전력 MOS 전류모드 논리 병렬 곱셈기 설계)

  • Kim, Jeong-Beom
    • Journal of IKEEE
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    • v.12 no.4
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    • pp.211-216
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    • 2008
  • This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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