• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• Journal of IKEEE
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• v.25 no.1
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• pp.218-228
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• 2021

This paper presents the high-efficiency DC-DC converter using the multi-resonant-circuit. The proposed converter has the power topology of half-bridge and utilizes the multi-resonant-circuit that is composed of 2 inductors (LL) and 1 capacitor (C) to achieve high-efficiency. The multi-resonant-circuit forms each resonant circuit of series circuit type with each resonant frequency, according to the operation modes. This paper first describes the operation pirinciples of proposed converter by the operation modes and steady-state fundamental approximation modelling. Then it shows a design example of the proposed converter based on the principles. And it is validated that the proposed converter has the operation characteristics of high-efficiency DC-DC power conversion through the experimental results of prototype converter implemented by the designed circuit parameters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.9
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• pp.882-888
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• 2002

This paper proposed a bias stability circuit that compensates the degradation of MMIC's performance for the variation of the process and temperature. The proposed bias circuit proved the superior effect compared with the conventional bias circuit using the constant current source. It designed and fabricated simultaneously two amplifier on one layout for comparison in same conditions. One is amplifier with conventional bias circuit using constant current source and the other is amplifier with proposed bias stability circuit. The chip was measured the microwave performances under process variation that classed the level NOM, MIN and MAX. The amplifier with a conventional bias circuit using constant current source has 6.4 dB gain variation and 7 mA Ids variation at 1.8 GHz, but the amplifier with the proposed bias circuit has the 2.1 dB gain variation and 3 mA Ids variation. As the result, MMIC having the proposed bias circuit shows the superior compensation of the quiescent point than the MMIC having the conventional bias circuit under the variations of the process and temperature and can improve the yield of the MMIC. The fabricated chip size is 1.2 mm $\times$ 1.4 mm.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.42-49
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• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.6
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• pp.7-11
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• 1976

A voltage-stable negative resistance circuit with operational amplifier is proposed, and circuit analysis is given all the input voltage range. The behavior of the v-i characteristics in the nogative resistance region is devided into two causes, and top points in the input v-i characteristics of the circuit is analyzed with them. Experimental results of the v-i characteristics of the proposed circuit has a good linearity in the negative region with negative resistance, -86$\Omega$~-833$\Omega$ for the input voltage, $\pm$ 1~$\pm$ 5 colts. The v-i characteristics of the circuit in all the input voltage range is discussed.

• Current Optics and Photonics
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• v.4 no.5
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• pp.434-440
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• 2020

Based on single-mode rate equations, we present an improved equivalent-circuit model for distributed-feedback (DFB) lasers that accounts for the effects of parasitic parameters and nonradiative recombination. This equivalent-circuit model is composed of a parasitic circuit, an electrical circuit, an optical circuit, and a phase circuit, modeling the circuit equations transformed from the rate equations. The validity of the proposed circuit model is verified by comparing simulation results to measured results. The results show that the slope efficiency and threshold current of the model are 0.22 W/A and 13 mA respectively. It is also shown that increasing bias current results in the increase of the relaxation-oscillation frequency. Moreover, we show that the larger the bias current, the lower the frequency chirp, increasing the possibility of extending the transmission distance of an optical-fiber communication system. The results indicate that the proposed circuit model can accurately predict a DFB laser's static and dynamic characteristics.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1348-1354
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• 2015

In this paper, chaotic circuit of the voltage controlled Lorentz system for engineering applications has been designed and implemented in an electronic circuit. The proposed circuit consists of MOS variable resistor, multipliers, capacitors, fixed resistors and operational amplifiers. The circuit was analysed by PSPICE program. PSPICE simulation results show that chaotic dynamics of the circuit can be controlled by the MOS variable resistor through time series analysis, frequency analysis and phase diagrams. Also, we implemented the proposed circuit in an electronic hardware system with discrete elements. Measured results of the circuit showed controllability of the circuit using the MOS resistor.

• Journal of Welding and Joining
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• v.34 no.3
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• pp.40-46
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• 2016

The digital controlled SMA welding power source having the hot start current and short circuit waveform control was developed. The inverter power controller was used an analog circuit and the short circuit waveform controller was developed using a 8-bit MCU. For the evaluation of the developed SMA welding power source it were compared with a domestic welding power sources. Using the high titanium oxide type and low hydrogen type electrodes, the characteristics of hot start and short circuit was evaluated. Developed SMA welding power source shows good start performance. Also, arc stability and low current weldability were improved by the short circuit waveform control.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.73-77
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• 2003

This paper presents a high-speed algorithmic analog-to-digital converter (ADC), which is based on gray coding. The realization method makes use of a two-input maximum circuit to provide a high-speed operation and a low-distortion in the transfer characteristic. The proposed ADC based on the CMOS integrated circuit technique is simple and suitable for implementing a highresolution ADC. The performances of the proposed circuit were studied using the PSPICE analog simulation program. The simulation-results verifying the circuit performances are agreed with the expected values.