• Journal of the Microelectronics and Packaging Society
• /
• v.10 no.4
• /
• pp.81-86
• /
• 2003

Electromigration of Sn-3.5Ag solder bump was investigated using flip chip specimens which consisted of upper Si chip and lower Si substrate. While the resistance of the flip chip sample did not almost change until the time right before the failure, the resistivity increased abruptly at the moment when complete failure of the solder joint occurred in the flip chip sample. At current densities of $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$, the activation energy for electromigration of the Sn-3.5Ag solder bump was characterized as ∼0.7 eV. Failure of the Sn-3.5Ag solder bump occurred at the solder/UBM interface due to the formation and propagation of voids at cathode side of the solder bump.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.57 no.10
• /
• pp.1841-1846
• /
• 2008

In this paper, we present the fabrication of microlens by electrohydrodynamic atomization(EHDA) of PDMS prepolymer. The diameter and contact angle of PDMS microlens can be altered by changing the applied voltage and substrate temperature at the experimental setup. It is considered that PDMS microlens can be integrated into the Lab-on-a-chip directly without any photolithographic process by EHDA. The property of PDMS microlens is confirmed by transmitting and measuring the Gaussian beam through microlens.

• KSBB Journal
• /
• v.21 no.5
• /
• pp.325-330
• /
• 2006

This study presents the characterization of an integrated portable microfluidic electrical detection system for fast and low volume immunoassay using polystyrene microbead, which are used as immobilization surfaces. In our chip, a filtration method using the microbead was adopted for sample immobilization and immunogold silver staining(IGSS) was used to increase the electrical signal. The chip is composed of an inexpensive and biocompatible Polydimethylsiloxane(PDMS) layer and Pyrex glass substrate. Platinum microelectrodes for electric signal detection were fabricated on the substrate and microchannel and pillar-type microfilters were formed in the PDMS layer. With a fabricated chip, we reacted antigen and antibody according to the procedures. Then, silver enhancer was injected to increase the size of nanogold particles tagged with the second antibody. As a result, microbeads were connected to each other and formed an electrical bridge between microelectrodes. Resistance measured through the electrodes showed a difference of two orders of magnitude between specific and nonspecific immuno-reactions. The detection limit was 10 ng/ml. The developed immunoassay chip reduced the total analysis time from 3 hours to 50 min. Fast and low-volume biochemical analysis has been successfully achieved with the developed microfilter and immuno-sensor chip, which is integrated to the microfluidic system.

• Journal of the Korean Society for Precision Engineering
• /
• v.20 no.10
• /
• pp.183-190
• /
• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2005.10a
• /
• pp.763-768
• /
• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.21-26
• /
• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• Journal of Microbiology and Biotechnology
• /
• v.16 no.8
• /
• pp.1229-1235
• /
• 2006

A lab-on-a-chip (LoC) was designed for simultaneous monitoring of microorganisms, antibiotic residues, somatic cells, and pH in raw milk. The LoC was fabricated from polydimethylsiloxane (PDMS) using microelectromechanical system (MEMS) technology, which consisted of two parts; a protein array and microchannel. The protein array was fabricated by immobilizing five types of antibodies corresponding to two microorganisms, two antibiotic residues, and somatic cells. A sol-gel film was deposited on a glass substrate to immobilize the antibodies. The target analytes in raw milk could be bound with the corresponding antibody by an immunoreaction, and the antigen-antibody complex was detected using fluorescence microscopy. SNARF-dextran was used as a pH indicator, and the SNARF-entrapped hydrogel was attached to the microchannel in the chip. After injecting the milk sample into the channel, the pH was measured by monitoring the change in fluorescence intensity by fluorescence microscopy. The on-chip simultaneous assay of two microorganisms (E. coli O157:H7 and Streptococcus agalactiae), two antibiotic residues (penicillin G and dihydrostreptomycin), and neutrophils was successfully accomplished using the proposed LoC system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.6
• /
• pp.595-601
• /
• 2013

This paper presents an optimized design of a millimeter-wave on-chip dipole antenna using CMOS process. The serious flaw of the antenna using CMOS process is low radiation efficiency because of high permittivity and conductivity. To overcome the weakness, we need to widen radiation area in air and optimize distance between an antenna and a reflector. The radiation efficiency and bandwidth of the designed antenna are respectively 16.5 % and 22.3 % at 80 GHz. Systematic methods are attempt to analyze an effect on the antenna radiation efficiency. To widen radiation area in air, substrate cut angle and distance between the antenna and chip edge are adjusted. In addition, to optimize distance between an antenna and reflector, substrate thickness and distance between the antenna and a circuit ground plane are adjusted.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.3
• /
• pp.53-57
• /
• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.2
• /
• pp.55-59
• /
• 2015

Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.