• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1001-1004
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• 2007

휴대폰, MP3 플레이어 등의 모바일 기기가 일반화되고 SoC(System-on-a-Chip) 기술이 발전하면서 모바일 콘텐츠의 이용 및 모바일 DRM(디지털 저작권 관리)에 대한 관심이 증가되었다. 모바일 기기의 경우 한정된 컴퓨팅 자원으로 인해 큰 멀티미디어 파일에 대한 암호화 연산의 오버헤드가 크며 그에 따른 전력 에너지 소모 또한 큰 부담이 된다. 본 논문에서는 모바일 환경에서 대상 데이터의 중요도 및 자원의 상태에 따라 에너지 소모를 줄일 수 있는 적응형 암호화 기법에 대해 제안한다. 제안하는 주요 방법으로, 저가의 콘텐츠에 대해서는 부분 암호화 기법 적용, 중간 가격 파일에 대한 다중 암호 방식의 적용, 모바일 기기의 사양에 따라 서로 다른 암호화 기법의 적용, 통신 상태나 배터리 용량에 따른 암호화 기법의 적용 등이 있다.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.27-33
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• 1993

This paper presents the &tal controller for driving high frequency voltage fed PWM inverter that carrier frequency is over 2OkHz.We analyzed the conventional PWM to select a proper PWM pattern. as the result, obtained PWM pattern of the controller in which asynchronus staircase sinusoidal waveform is used as reference signal, and variable carrier ratio method was used for PWM control. The PWM controller is designed by fully digital method. Especially, Thk proposed controller is consisted of 8 bit one-chip microprocessor and digital logic. the former is for arithmetic and data processing, and the latter is for PWM pattern synthesis. Therefore, The responsibility and controllability is improved. Also, Data processing capability is improved using proper program to output modulation index with 9 bits. Circuits configuration of digital controller are made up of one chip 8051 and EPLD, and its controllability is tested by operating voltage fed inverter. Harmonics and current waveform is evaluated and analyzed for the voltage fed inverter system.

• Journal of Korea Multimedia Society
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• v.4 no.3
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• pp.257-269
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• 2001

Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• The Journal of the Korea institute of electronic communication sciences
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• v.15 no.3
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• pp.487-494
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• 2020

In this paper, we propose a current memory circuit design that reduces static power consumption and maximizes the advantages of current mode signal processing. The proposed current memory circuit minimizes the problem in which the current transfer error increases as the data transfer time increases due to clock-feedthrough and charge-injection of the existing current memory circuit. The proposed circuit is designed to insert a support MOS capacitor that maximizes the Miller effect in the current transfer structure capable of low-power operation. As a result, it shows the improved current transfer error according to the memory time. From the experimental results of the chip, manufactured with MagnaChip / SK Hynix 0.35 process, it was verified that the current transfer error, according to the memory time, reduced to 5% or less.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.158-162
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• 2012

In this paper, we propose a wireless modem, which used OFDM/64QAM method and the ISM band with 2.4GHz radio frequency. In this paper proposed the case of a modem, the main program to process the baseband processor, processing speed, operating voltage, and reliability should be ensured. So we have designed with Ralink's RT2870, witch was used for Wi-Fi solution. The RT2870 provides full support for wireless LAN standard, and supports various modulation formats, 2.4GHz and 5GHz bands, both of which support chip. In this paper, we also output the modulated signal transmitted wirelessly to the 2.4GHz band RF RT2850 chip processing was applied and using 40MHz band 2.422 ~ 2.462GHz wireless bands were designed to occupy. By applying bi-directional transmission between wireless transmitter and receiver, it can be effectively connected with any kinds of wireless LAN with 2.4GHz ISM band. Therefore it could economically be used as peripheral equipments for POS system or personal wireless device based on Android platform.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.2
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• pp.146-153
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• 2008

Integrated humidity sensor system with two stages operational amplifier has been designed and fabricated by $0.8{\mu}m$ analog mixed CMOS technology. The system (28 pin and $2mm{\times}4mm$) consisted of Wheatstone-bridge type humidity sensor, resistive type humidity sensor, temperature sensors and operational amplifier for signal amplification and process in one chip. The poly-nitride etch stop process has been tried to form the sensing area as well as trench in a standard CMOS process. This modified technique did not affect the CMOS devices in their essential characteristics and gave an allowance to fabricate the system on same chip by standard process. The operational amplifier showed the stable operation so that unity gain bandwidth was more than 5.46 MHz and slew rate was more than 10 V/uS, respectively. The drain current of n-channel humidity sensitive field effect transistor (HUSFET) increased from 0.54 mA to 0.68 mA as the relative humidity increased from 10 to 70 %RH.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.