• 융합신호처리학회논문지
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• 제10권2호
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• pp.120-126
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• 2009

반도체 외관결함에는 발생 요인이 각각 다른 crack, foreign material, chip-out, chip, void 등이 있으며, 검사 시스템에서는 결함 유무 및 결함 분류를 수행하여 효과적인 공정관리가 가능하여야 한다. 본 논문에서는 QFN 패키지 결함의 분류를 위한 알고리즘 및 광학시스템을 제안한다. 제안한 방법에서 분류가 어려운 결함 중 하나인 foreign material 과 chip의 효과적인 분류를 위해 제안한 결함의 위치, 밝기의 특징정보(feature)를 사용한 ML(Maximum Likelihood ratio) 분류방법 및 특징정보 획득에 효과적인 광학계를 제안하였다. 실험 결과에서 분류가 어려운 foreign material과 chip에 대한 신뢰성 높은 분류성능을 보였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.31-32
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• 2006

A signal conditioning circuit for capacitive sensors was developed using a commercial single chip solution. Since capacitive displacement sensors can achieve high resolution and linearity, they have been widely used as precision sensors within the range of several hundred micrometers. However, they inherently have a limitation in low frequency range and some nonlinearity characteristics and so a specially designed signal conditioning circuit is needed to handle these properties. Up to now, several companies already have succeeded in the development of the capacitive sensors system and they are commercially available in the market. In this research, to construct the signal processing circuits more easily and simply, we used a universal LVDT signal conditioner (AD698). Since the AD698 provides one chip solution for a basic signal processing including modulation and demodulation using various internal components, we can build the processing circuits successfully with minimal additional circuits: a compensation circuits for the drift caused by the bias current of OP amplifiers and a fine adjustment circuit for the elimination of nonlinearity. The signal processing circuits shows nonlinearity less than 0.05% in the comparison with a laser interferometer.

• 센서학회지
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• 제15권2호
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• pp.112-119
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• 2006

Resolution of an image sensor is very significant parameter to improve. It is hard to improve the resolution of the CMOS vision chip for edge detection based on a biological retina using a resistive network because the vision chip contains additional circuits such as a resistive network and some processing circuits comparing with general image sensors such as CMOS image sensor (CIS). In this paper, we proved the problem of low resolution by separating photo-sensing and signal processing circuits. This type of vision chips occurs a problem of low operation speed because the signal processing circuits should be commonly used in a row of the photo-sensors. The low speed problem of operation was proved by using a reset decoder. A vision chip for edge detection with $128{\times}128$ pixel array has been designed and fabricated by using $0.35{\mu}m$ 2-poly 4-metal CMOS technology. The fabricated chip was integrated with optical lens as a camera system and investigated with real image. By using this chip, we could achieved sufficient edge images for real application.

• 전기학회논문지
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• 제58권7호
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• pp.1418-1423
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• 2009

This paper describes the design and implementation of a System-on-a-Chip (SoC) for image processing applications to use in wearable/mobile products. The target Soc consists of LEON 2 core, AMBA/APB bus-systems and custom-designed controllers. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, an image processing application is performed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권2호
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.

• 센서학회지
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• 제13권3호
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• pp.188-194
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• 2004

With a remarkable advance in CMOS (complimentary metal-oxide-semiconductor) process technology, a variety of vision sensors with signal processing circuits for complicated functions are actively being developed. Especially, as the principles of signal processing in human retina have been revealed, a series of vision chips imitating human retina have been reported. Human retina is able to detect the edge and motion of an object effectively. The edge detection among the several functions of the retina is accomplished by the cells called photoreceptor, horizontal cell and bipolar cell. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge and motion detection. The designed vision chip was fabricated using $0.6{\mu}m$ CMOS process and the characteristics were measured. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.286-292
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• 2004

In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks are mapped. To apply it to multitask applications, the concurrent execution of the function blocks of different tasks also should be considered. Since tasks are scheduled independently, considering all cases of concurrency in each processing element is impractical. Therefore we make an average estimate on the effects of other tasks with respect to bus request rate and bus access time. The proposed technique was incorporated with our exploration framework for on-chip bus architectures, Its viability and efficiency are validated by a preliminary example.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Journal of Forest and Environmental Science
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• 제25권1호
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• pp.75-84
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• 2009

This study was conducted to investigate the physical properties of wood chip for fuel processing with woody biomass. Seven species are selected and processed for testing physical properties by 3-type wood chippers which are commonly used in Korea. Wood chips produced by self-propelled drum chipper and fixed type wood chipper equipped with separator were uniform in size and shape. It was shown that the bulk density of produced wood chips was decreased with increasing the wood chip layer thickness, and oak chips prepared by self-propelled drum chipper and fixed type wood chipper showed the highest bulk density.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.572-578
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• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.