• Proceedings of the KWS Conference
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• 2007.11a
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• pp.218-221
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• 2007

The surface mounting technology of 0402 electric chip part is necessary to fabricate a high density and multi-functional module, but there is a limitation of the technology, like as a bridge and self-alignement. This work estimated SMT processing factors of 0402 chip. To obtain optimum SMT process, we evaluated effects of stencil thickness, shape of hole on printability and mountability. Printability shows best results under the thickness of $80{mu}m$ with circle hole shape and 90% square hole shape. In case of chip mounting process, chip mis-alignment and bridge was occurred rarely in same conditions. In more thin stencil thickness, $50{mu}m$, strength of 1005 chip parts was poor, because of amount of printed solder was insufficient.

• Journal of Sensor Science and Technology
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• v.18 no.3
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• pp.190-196
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• 2009

In a conventional camera system, a target tracking system consists of a camera part and a image processing part. However, in the field of the real time image processing, the vision chip for edge detection which was made by imitating the algorithm of humanis retina is superior to the conventional digital image processing systems because the human retina uses the parallel information processing method. In this paper, we present a high speed target tracking system using the function of the CMOS vision chip for edge detection.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1081-1090
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• 1988

A series of procedures using image processing techniques is presented for extracting layout information fast and automatically from chip images. CIF (caltech intermediate form) is chosen for representing such information. First, line-edges are extracted using a line-edge detector. Then, thinning and noise removal procedures follow. Subsequent procedures are vertex extraction and vertex grouping. Finally, CIF is extracted from the coordinates of the grouped vertices. In this paper, the final process is applied to only metal layer. In experiments, this processing scheme is shown to be very effective in extracting CIF.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.08a
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• pp.261-264
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• 2000

본 논문에서는 이동 통신용 단말기에 주로 사용되는 RF-chip inductor의 자동 외관검사를 위한 시스템 개발에 필요한 알고리즘을 제안하였다. 본 논문에서 제안한 방법은 영상취득 후 처리과정에서 동적 이진화 방법, 가산투영 등 영상처리에 관련된 방법을 이용해 코일 부분과 코어부분을 분리한 후 세선화 방법, 라벨링 방법 등을 적용하여 분리된 코일부분에 대해 코일의 감긴 회수와 피치간격의 불균일 검사를 수행하고 기준값 이상의 오차를 갖는 소자를 불량으로 처리하는 보다 개선된 처리방법을 제안하였으며 모의실험을 통해 성능을 검증하였다.

• Proceedings of the Plant Resources Society of Korea Conference
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• 2023.04a
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• pp.25-25
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• 2023

As the demand for processing potatoes increases, imports of raw potatoes and potato products are increasing, so it is necessary to expand potato production as raw materials for processing in Korea. Potato varieties for processing that can be grown in fall have been developed, but research on cultivation technology and processing quality management technology to improve chip processing quality is very insufficient. Therefore, this study was conducted to investigate the optimal harvest time by investigating the quantity and chipping characteristics of potato chips during autumn cultivation. As the test varieties, the chip processing varieties "Saebong", "Eunsun", and "Geumnaru" were used, and the potato cultivation site was the Seocheon-gun Test field (214 Gaeya-ri) of the Chungcheongnam-do. The test treatment was at harvest time after spring cultivation, and the potatoes were harvested at 70, 80, 90, and 100 days after sowing based on the sowing time. The investigation items were potato productivity (total yield, yield of standard processing, and number of tubers) and chip-processing characteristics (chip color, dry matter content, glucose content, etc.). As a result of examining the yield characteristics according to the harvest time, statistical significance was not found according to the treatment. The total yield (ton/ha) was 27.5 to 30.5, and there was no significant difference depending on the time of 70 to 100 days after harvest. The standard quantity for processing (yield of 81-250g potatoes per unit) also showed a similar trend. In chipping characteristics according to harvest time, statistical significance was high in specific gravity and glucose content. The specific gravity was highest at 1.077 at 70 days after harvest, and the glucose (mg/dL) content was the lowest at 37.5 at 80 days after harvest. Statistical significance was not recognized, but chip color (L value) was the highest at 64.4 at 70 days after harvest. Therefore, it is judged that the optimal harvesting time for chip processing is 70 to 80 days after sowing.

• Journal of Welding and Joining
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• v.26 no.3
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• pp.30-36
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• 2008

A flip-chip bonding system using IR laser with a wavelength of 1064 nm was developed and associated process parameters were analyzed using Taguchi methods. An infrared laser beam is designed to transmit through a silicon chip and used for transferring laser energy directly to micro-bumps. This process has several advantages: minimized heat affect zone, fast bonding and good reliability in the microchip bonding interface. Approximately 50 % of the irradiated energy can be directly used for bonding the solder bumps with a few seconds of bonding time. A flip-chip with 120 solder bumps was used for this experiment and the composition of the solder bump was Sn3.0Ag0.5Cu. The main processing parameters for IR laser flip-chip bonding were laser power, scanning speed, a spot size and UBM thickness. Taguchi methods were applied for optimizing these four main processing parameters. The optimized bump shape and its shear force were modeled and the experimental results were compared with them. The analysis results indicate that the bump shape and its shear force are dominantly influenced by laser power and scanning speed over a laser spot size. In addition, various effects of processing parameters for IR laser flip-chip bonding are presented and discussed.

• Korean Journal of Food Science and Technology
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• v.14 no.4
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• pp.364-369
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• 1982

Two varieties of potatoes, Irish cobbler and Shimabara stored for seven and nine months respectively by irradiation combined with natural low temperature (year-round temperature change:$2{\sim}17^{\circ}C)$ on a batch scale were investigated on the suitability for processing of potato chip. Nine months after storage, irradiated potatoes (Irish cobbler) tended to maintain somewhat-better texture and sensory quality than untreated in potato chip processing. Peel rate, closely related to potato chip yield, of untreated potatoes were $20{\sim}25%$ higher than those of irradiated and Agtron color determination of potato chip from both irradiated were commercially acceptable. Preservation of potatoes by irradiation combined with natural low temperature was evaluated as an alternative method of the supply for raw materials of potato chip processing in the off season in Korea.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.11 no.4
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• pp.147-153
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• 2012

The demands of the large scale machine tools, for instance, such as planomiller, turning machine, boring machine, NC machine, have been gradually increased in recent years. As the performances of machine tools and/or cutting tools are advanced, it is possible to perform high-speed and high-precision cutting works. The effective treatment of wet chip, which is discharged from cutting works, becomes very important problems. Therefore, this study is forced on the design of large scale machine tools using CATIA V5R18 and analysis of cutter, which is considered as essential equipment in large scale machine tools, using MSC.Nastran & MSC.Patran. Especially, the relations between tolerated load of cutter, driving horse power and rpm of driving shaft in chip processing system are investigated through analysis. As the results, the reliability of design could be improved by evaluating simulated numerical values, it showed that tolerated loads of supported part and edged part of cutter are 87,000N and 14,450N, respectively.

• ETRI Journal
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• v.27 no.5
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• pp.539-544
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• 2005

An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with $128{\times}128$ pixels, was below 20mW. The vision chip was designed using $0.25{\mu}m$ 1-poly 5-metal standard full custom CMOS process technology.

• Geomechanics and Engineering
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• v.15 no.3
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• pp.811-822
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• 2018

Chip size distribution can be used to evaluate the cutting efficiency and to characterize the cutting behavior of rock during cutting and fragmentation process. In this study, a series of linear cutting tests was performed to investigate the effect of cutting conditions (specifically cut spacing and penetration depth) on the production and size distribution of rock chips. Linyi sandstone from China was used in the linear cutting tests. After each run of linear cutting machine test, the rock chips were collected and their size distribution was analyzed using a sieving test and image processing. Image processing can rapidly and cost-effectively provide useful information of size distribution. Rosin-Rammer distribution pamameters, the coarseness index and the coefficients of uniformity and curvature were determined by image processing for different cutting conditions. The size of the rock chips was greatest at the optimum cut spacing, and the size distribution parameters were highly correlated with cutter forces and specific energy.