• 한국광학회:학술대회논문집
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• 한국광학회 2001년도 제12회 정기총회 및 01년도 동계학술발표회
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• pp.206-207
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• 2001

The photorefractive (PR) effect in liquid crystals sandwiched between photoconductive polymer layers was first studied by Ono et al. They reported that the PR effect vanished at steady state If there were not insulating layers because no charge trapping occurred in the photoconductive poly(N-vinylcarbazole) (PVK) layers. However we observed a significant PR effect in the polymer layered liquid crystal (PLLC) system where a liquid crystal layer doped with fullerene is sandwiched between two photoconductive PVK layers. (omitted)

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• 대한전자공학회논문지SD
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• 제45권7호
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• pp.37-43
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• 2008

본 논문에서는 전하 펌프 방법 (Charge Pumping Method, CPM)를 이용하여 서로 다른 질화막 층을 가지는 N-Channel SANOS (Silicon-$Al_2O_3$-Nitride-Oxide-Silicon) Flash Memory Cell 트랜지스터의 트랩 특성을 규명하였다. SANOS Flash Memory에서 계면 및 질화막 트랩의 중요성은 널리 알려져 있지만 소자에 직접 적용 가능하면서 정화하고 용이한 트랩 분석 방법은 미흡하다고 할 수 있다. 기존에 알려진 분석 방법 중 전하 펌프 방법은 측정 및 분석이 간단하면서 트랜지스터에 직접 적용이 가능하여 MOSFET에 널리 사용되어왔으며 최근에는 MONOS/SONOS 구조에도 적용되고 있지만 아직까지는 Silicon 기판과 tunneling oxide와의 계면에 존재하는 트랩 및 tunneling oxide가 얇은 구조에서의 질화막 벌크 트랩 추출 결과만이 보고되어 있다. 이에 본 연구에서는 Trapping Layer (질화막)가 다른 SONOS 트랜지스터에 전하 펌프 방법을 적용하여 Si 기판/Tunneling Oxide 계면 트랩 및 질화막 트랩을 분리하여 평가하였으며 추출된 결과의 정확성 및 유용성을 확인하고자 트랜지스터의 전기적 특성 및 메모리 특성과의 상관 관계를 분석하고 Simulation을 통해 확인하였다. 분석 결과 계면 트랩의 경우 트랩 밀도가 높고 trap의 capture cross section이 큰 소자의 경우 전자이동도, subthreshold slop, leakage current 등의 트랜지스터의 일반적인 특성 열화가 나타났다. 계면 트랩은 특히 Memory 특성 중 Program/Erase (P/E) speed에 영향을 미치는 것으로 나타났는데 이는 계면결함이 많은 소자의 경우 같은 P/E 조건에서 더 많은 전하가 계면결함에 포획됨으로써 trapping layer로의 carrier 이동이 억제되기 때문으로 판단되며 simulation을 통해서도 동일한 결과를 확인하였다. 하지만 data retention의 경우 계면 트랩보다 charge trapping layer인 질화막 트랩 특성에 의해 더 크게 영향을 받는 것으로 나타났다. 이는 P/E cycling 횟수에 따른 data retention 특성 열화 측정 결과에서도 일관되게 확인할 수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Journal of Information Display
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• 제2권3호
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• pp.1-5
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• 2001

The effect of doping on the energy transfer and charge carrier trapping processes has been studied in organic light-emitting diodes (OLEDs) doped with a fluorescent laser dye. The devices consisted of N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1-biphenyl-4,4'-diamine (TPD) as a hole transporting layer, tris(8-hydroxyquinoline) aluminum ($Alq_3$) as the host, and a fluorescent dye, 4-dicyanomethylene-2-methyl-6-[2-(2,3,6,7-tetrahydro-1 H,5H-benzo[i,j]quinolizin-8-yl) vinyl]-4H-pyran) (DCM2) as the dopant. Temperature dependence of the current-voltage-luminescence (I-V-L) characteristics, the electroluminescence (EL) and photoluminescence (PL) spectra are studied in the temperature ranging between 15 K and 300 K. The emission from DCM2 was seen to be much stronger compared with the emission from $Alq_3$, indicative of efficient energy transfer from $Alq_3$ to DCM2. In addition, the EL emission from DCM2 increasd with increasing temperature while the emission from the host $Alq_3$ decreased. The result indicates that direct charge carrier trapping becomes efficient with increasing temperature. The EL emission from DCM2 shows a slightly sublinear dependence on the current density, implying the enhanced quenching of excitons at high current densities due to the exciton-exciton annihilation.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1418-1420
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• 2008

In this paper, the light emitting efficiency, spectrum, and the lifetime of the phosphorescent devices, whose emission characteristics are strongly dominated not only by the energy transfer but also by the charge carrier trapping induced by the emissive dopant, are explained by differences in the energy levels of the host, dopant, and nearby transport layers. On the basis of our finding on device performance and photocurrent measurement data by time-of-flight (TOF), we investigated the effect of the difference of carrier trapping dopant and properties of the host materials on the efficiency roll-off of phosphorescent organic light emitting diode (OLED), along with a physical interpretation and practical design scheme, such as a multiple host system, for improving the efficiency and lifetime of devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• Transactions on Electrical and Electronic Materials
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• 제16권4호
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.