• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.199-199
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• 2011

Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1301-1307
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• 2004

Reduced pressure chemical vapor deposition(RPCYD) technology has been investigated for the growth of SiGe epitaxial films with two dimensional in-situ doped boron impurities. The two dimensional $\delta$-doped impurities can supply high mobility carriers into the channel of SiGe heterostructure MOSFETs(HMOS). Process parameters including substrate temperature, flow rate of dopant gas, and structure of epitaxial layers presented significant influence on the shape of two dimensional dopant distribution. Weak bonds of germanium hydrides could promote high incorporation efficiency of boron atoms on film surface. Meanwhile the negligible diffusion coefficient in SiGe prohibits the dispersion of boron atoms: that is, very sharp, well defined two-dimensional doping could be obtained within a few atomic layers. Peak concentration and full-width-at-half-maximum of boron profiles in SiGe could be achieved in the range of 10$^{18}$ -10$^{20}$ cm$^{-3}$ and below 5 nm, respectively. These experimental results suggest that the present method is particularly suitable for HMOS devices requiring a high-precision channel for superior performance in terms of operation speed and noise levels to the present conventional CMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.76-81
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• 2007

Threshold voltage ($V_{th}$) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length ($x_h$) in the channel which is related to the barrier lowering becomes very important. A fitting parameter ${\delta}_w$ was introduced semi-empirically with the fin body width and body doping concentration for higher accuracy. The $V_{th}$ model predicted well the $V_{th}$ behavior with fin body thickness, body doping concentration, and gate length. Our compact model makes an accurate $V_{th}$ prediction of DG devices with the gate length up to 20-nm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.3
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• pp.541-546
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• 2008

In this paper, conduction phenomena have been considered for nano structure double gate MOSFET, using the analytical model. The Possion equation is used to analytical model. The conduction mechanisms to have an influence on current conduction are thermionic emission and tunneling current, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. The deviation of current path and the influence of current path on subthreshold swing have been considered according to the dimensional parameters of double gate MOSFET, i.e. gate length, gate oxide thickness, channel thickness. The optimum channel doping concentration is determined as the deviation of conduction path is considered according doping concentration.

• ETRI Journal
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• v.39 no.2
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• pp.284-291
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• 2017

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.7
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.457-460
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• 1999

The effects of electrical positive stress on n-channel LDD and offset structured poly-Si TFT\`s have been systematically investigated in order to analyze the transfer curve\`s shift mechanism. It has been found that the LDD and offset regions behave as a series resistance that reduce the electric field near drain. Hot carrier effects are reduced because of these results. After electrical stress transfer curve’s shift and variation of the off-current are dependent upon the offset length rather than offset region’s doping concentration. Variation of the subthreshold slope is dependent upon offset region’s doping concentration as well as offset length.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.285-287
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• 2016

이황화 몰리브덴(Molybdenum disulfide: $MoS_2$)을 채널(Channel) 물질로 이용하여 metal-oxide-semiconductor(MOS) 구조를 제작하고, 효율적인 제작과정을 제시하였고 특히, Source/Drain의 Doping concentration을 조절하여 효과적인 $MoS_2$ Transistor를 제작 및 시뮬레이션 하였다. 그 후 여러 MOSFET의 특성 분석을 통하여 소자로서의 기능을 확인해보았다. 그리고 특히 채널의 전기적인 특성을 분석하고 채널 내 그리고 contact 사이의 저항 및 mobility의 특성을 알아보았는데, 그 중 Source/Drain Doping Effect와 performance 분석을 통해, 최적화된 $MoS_2$ Transistor를 찾아보았다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.527-528
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• 2017

Current-voltage characteristics of source-overlapped gate tunnel field-effect transistor (SOG-TFET) with different channel doping concentration are proposed. Due to the gaussian doping in which the channel region near the source is highly doped and that far from the source is lightly doped, the ambipolar current was reduced, compared with the uniformly-doped SOG-TFET. On-current is almost similar in P-P-N and P-I-N structure but subthreshold swing (SS) of P-P-N TFET enhanced 5 times higher than those of P-I-N TFET. off-current and ambiploar current of the proposed SOG-TFET decrease 10 times and 100 times than those of the uniformly-doped SOG-TFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.709-712
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• 2012

In this paper, current-voltage have been considered for DGMOSFET, using the analytical model. The Possion equation is used to analytical. Threshold voltage is defined as top gate voltage when drain current is $10^{-7}A$. Investigated current-voltage characteristics of channel length changed length of channel from 20nm to 100nm. Also, The changes of current-voltage have been investigated for various channel thickness and doping concentration using this model, given that these parameters are very important in design of DGMOSFET. The deviation of conduction path and the influence of conduction path on current-voltage have been considered according to the dimensional parameters of DGMOSFET.