• Title/Summary/Keyword: capacitor model

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A Study on the Implementation of Optimized Dechucking System (최적 dechucking 시스템 구현에 관한 연구)

  • Seo, Jong-Wan;Suh, Hee-Seok;Shin, Myong-Chul
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.5
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    • pp.106-111
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    • 2007
  • After the semiconductor processing, wafer is attracted by ESC(Electrostatic Chuck) with remaining electric charge. That causes too many problems for examples, sliding of wafer, popping or broken. This paper presents the model of ESC for silicon wafer, which is modeled by electrical circuit component such as capacitor. The simulations using PSpice result in the phenomenon of silicon wafer was charged by ESC. In this paper we suggest the discharging method. for wafer.

Design and Implementation of Double Down-Converter for Satellite TV (위성 TV용 이중 하향 변환기의 설계 및 제작)

  • Lee, Seung-Dae
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.2
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    • pp.840-845
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    • 2013
  • In this paper, the broadband frequency double down-converter based on LC filter technologies has been designed and implemented, and its performances are introduced. The Designed frequency double down-converter is consisted with a low-noise amplifier, mixer, IF amplifier, LC filter, DC-block capacitor and RF-bypass capacitor. Especially, instead of active devices of a typical converter, the suggested converter designed using passive devices to provide both low-power consumption and low-cost model. As results of the measurement, the implemented frequency double down-converter realizes the broadband performance with the bandwidth of 100MHz (13~113MHz) at the center frequency of 63MHz, and its gain is approximately 40dB.

A Study of MPPT Control Algorithm for Boost Converter of Photovoltaic System Considering Capacitor Equivalent Series Resistance (커패시턴스 내부저항을 고려한 태양광용 Boost 컨버터에 대한 MPPT 제어 알고리듬 고찰)

  • Choi J. Y.;Yu G. J.;Lee D. G.;Lee K. O.;Jung Y. S.;Kim K. H.
    • Proceedings of the KIPE Conference
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    • 2001.12a
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    • pp.109-114
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    • 2001
  • Photovoltaic systems normally use a maximum power point tracking (MPPT) technique to continuously deliver the highest possible power to the load when variations in the insolation and temperature occur. A simple method of tracking the maximum power points (MPPs) and forcing the boost converter system to operate close to these points is presented through deriving small-signal model and transfer function of boost converter. This paper aims at modeling boost converter including equivalent series resistance of input reservoir capacitor by state-space-averaging method. In the future, properly designed controller for compensation will be constructed for maximum photovoltaic power tracking control.

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An Accelerated Degradation Test of Electric Double-Layer Capacitors (전기이중층커패시터의 가속열화시험)

  • Jung, Jae-Han;Kim, Myung-Soo
    • Journal of Applied Reliability
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    • v.12 no.2
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    • pp.67-78
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    • 2012
  • An electric double-layer capacitor(EDLC) is an electrochemical capacitor with relatively high energy density, typically hundreds of times greater than conventional electrolytic capacitors. EDLCs are widely used for energy storage rather than as general-purpose circuit components. They have a variety of commercial applications, notably in energy smoothing and momentary-load devices, and energy-storage and kinetic energy recovery system devices used in vehicles, etc. This paper presents an accelerated degradation test of an EDLC with rated voltage 2.7V, capacitance 100F, and usage temperature $-40^{\circ}C{\sim}65^{\circ}C$. The EDLCs are tested at $50^{\circ}C$, $60^{\circ}C$, and $70^{\circ}C$, respectively for 1,750hours, and their capacitances are measured at predetermined times by constant current discharge method. The failure times are predicted from their capacitance deterioration patterns, where the failure is defined as 30% capacitance decrease from the initial one. It is assumed that the lifetime distribution of EDLC follows Weibull and Arrhenius life-stress relationship holds. The life-stress relationship, acceleration factor, and $B_{10}$ life at design condition are estimated by analyzing the accelerated life test data.

Low Power Digital Logic Gate Circuits Based on N-Channel Oxide TFTs (N-Channel 산화물 TFT 기반의 저소비전력 논리 게이트 회로)

  • Ren, Tao;Park, Kee-Chan;Oh, Hwan-Sool
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.3
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    • pp.1-6
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    • 2011
  • Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

The Controller Design of Bi-directional DC-DC Converter for a Fuel Cell Energy Storage System (연료전지용 커패시터 충.방전을 위한 양방향 DC-DC 컨버터 제어기 설계)

  • Kim, Seung-Min;Yang, Seung-Dae;Choi, Ju-Yeop;An, Jin-Woong;Lee, Sang-Chul;Lee, Dong-Ha
    • 한국태양에너지학회:학술대회논문집
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    • 2012.03a
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    • pp.222-228
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    • 2012
  • This paper presents a design and simulation of bi-directional DC/DC boost converter for a fuel cell system. In this paper, we analyze the equivalent model of both a boost converter and a buck converter. Also we propose the controller of bi-directional DC-DC converter, which has buck mode of charging a capacitor and boost mode of discharging a capacitor. In order to design a controller, we draw bode plots of the control-to-output transfer function using specific parameters and incorporate 3pole-2zero compensator in a closed loop. As a result, it has increased PM(Phase Margin) for better dynamic performance. The proposed bi-directional DC-DC converter's 3pole-2zero compensation method has been verified with computer simulation and simulation results obtained demonstrates the validity of the proposed control scheme.

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A Study on a Symmetric QMSA (대칭형 QMSA에 관한 연구)

  • Go, Yeong-Hyeok
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.5
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    • pp.33-41
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    • 2000
  • In this paper, a symmetric QMSA(Quarter-wavelength Microstrip Antenna) loading a capacitor to spread the electric flux lines is proposed. It was found that the bandwidth of this symmetric QMSA is broader than that of the asymmetric QMSA having a right-side Parallel plate only to load a capacitor. It was also found that this antenna could receive both vertically and horizontally polarized waves at 2.13GHz, and would be useful as a small antenna for wireless telephones and for indoor communication. A transmission line circuit model of this antenna was obtained and used to compute the resonant frequency and the return loss of the antenna accurately.

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Measurement of the indoor power line channel characteristic (옥내 전력선 통신 채널 특성 측정)

  • Heo, Yun-Seok
    • The Journal of Information Technology
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    • v.7 no.3
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    • pp.1-10
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    • 2004
  • Considerable efforts has been recently devoted to the determination of accurate channel models for the Power Line environment, both for the indoor and outdoor cases. The common denominator and limitation of the known and previously published models is the particular type of approach followed. In this paper is concerned with a power line channel modeling for the more fast and efficiently power line communication experiment. A capacitor load channel simulator is a essential equipment in the power line modem development for indoor network. We accomplished a channel modelling by the frequency response method about the total 224 capacitor load cases. On the basis of this measurement modeling it is here revealed that the PLC is a more deterministic media that commonly believed.

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3차원적 도핑 분포 측정을 위한 SCM 응용 방법 (The SCM Method for Three-Dimensional Dopant Profiles)

  • Lee Jun-Ha;Lee Hoong-Joo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.7 no.1
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    • pp.7-11
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    • 2006
  • Through SCM modeling, we found that the depletion layer in silicon was of a form of a spherical capacitor with the SCM tip biased. Two-dimensional (2D) finite differential method code with a successive over relaxation (SOR) solver has been developed to model the measurements by SCM of a semiconductor wafer that contains an ion-implanted impurity region. Then, we theoretically analyzed the spherical capacitor and determined the total depleted-volume charge Q, capacitance C, and the rate of capacitance change with bias dC/dV. It is very important to observe the depleted carriers' movement in the silicon layer by applying the bias to the tip. So, we calculated the depleted-volume charge, considering different factors such as tip size, oxide thickness, and applied bias (dc+ac), which have an influence on potential and depletion charges.

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Design of a Small Loop Microstrip Antenna to load Capacitors (용량을 장하한 미소 루프 마이크로스트립 안테나 설계)

  • Park Seong-Il;Ko Young-Hyuk
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2006.05a
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    • pp.637-640
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    • 2006
  • In this paper, a microstrip antenna with a small loop consisting of the left and right parallel plate to load capacitor is proposed. It is obtained the improved small size than the antenna of the transformed Uh and the antenna of the left and right parallel plate to load capacitor on QMSA. Equivalent circuit of transmission line model is designed to find more accurate resonant frequency. Also, the designed and fabricated antenna can receive both vertically and horizontally polarized waves to operating frequency of 1.5GHz. Therefore proposed antenna is available as a small antenna for wireless communication and will be quite useful for indoor communication

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